Interrupts & DMA

ACompressed recap

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Interrupts: device raises INTR; CPU finishes the current instruction, saves PC (next instruction) and PSW, disables interrupts, runs the ISR, returns with RTI. Vectored: table base + vector × entry size; non-vectored: ISR polls. Daisy chain = priority by position; masks; NMI. Interrupt CPU fraction = units/s × overhead; gain over busy-wait = time between units ÷ overhead. DMA: CPU sets up, controller transfers, one interrupt per block; burst / cycle stealing / transparent; overhead = CPU time per block ÷ block time; cycle stealing = stolen cycles ÷ bus cycles; burst blocking = Y/(X+Y); count limit ⌈S/2ᵏ⌉.

BMerged rule card

6.2.1 Interrupts: the interrupt cycle, ISR, context saving, vectored interrupts, priority and daisy chain

• Interrupt: finish current instruction → (if enabled) save PC (next instruction) and PSW → disable → ISR → RTI.
• Vectored: ISR address at table base + vector × entry size. Non-vectored: ISR polls devices.
• Daisy chain: priority by position. Mask register; NMI unmaskable; nesting by priority.

6.2.2 Interrupt-driven I/O: overhead per transfer; interrupts vs polling

• Interrupt CPU fraction = units/s × overhead per unit (cycles/f).
• Gain over busy-wait = time between units ÷ overhead.
• Scale by the device's active fraction for overall cost.
• Very fast block devices → DMA.

6.2.3 DMA: the controller, burst mode, cycle stealing, transparent mode; CPU time lost

• DMA: CPU programs address, count, direction; controller requests bus (HOLD), gets grant (HLDA), transfers, interrupts at the end.
• Burst (block), cycle stealing (word at a time), transparent (idle cycles only).
• Overhead fraction = CPU time per block ÷ block delivery time. Cycle stealing = stolen cycles/s ÷ bus cycles/s. Burst blocking = Y/(X + Y).
• k-bit count → ⌈S / 2ᵏ⌉ DMA operations.

CInterleaved GATE-style questions

Q1NAT1 markReturn address

Word-addressable; instructions at 500 (2 words), then 1, 1, 2 and 1 words. An interrupt arrives during the 4th instruction. Return address?

Numerical answer: ________

Q2NAT1 markVector

Vector table at address 0 with 4-byte entries. The ISR address for vector 33 is stored at which address?

Numerical answer: ________

Q3NAT2 marksGain

A device sends 1 byte every 80 µs; interrupt overhead 5 µs. Gain of interrupt mode over busy-waiting?

Numerical answer: ________

Q4NAT2 marksInterrupt fraction

A 500 MHz CPU; a device causes 50,000 interrupts per second, each costing 600 cycles. Percentage of CPU time?

Numerical answer: ________

Q5NAT2 marksDMA overhead

DMA from a 20 MB/s (decimal) device in 40,000-byte blocks; the 800 MHz CPU spends 1,600 cycles per block. Percentage of CPU time?

Numerical answer: ________

Q6NAT2 marksCount register

A 16-bit byte count register; a file of 1,000 KB (1,024,000 bytes). Minimum number of DMA operations?

Numerical answer: ________

Q7MCQ1 markDMA mode

Which DMA mode never slows the CPU?

• (A) Cycle stealing
• (B) Block
• (C) Transparent
• (D) Burst

Q8MSQ2 marksPriority

Which are true?

• (A) A vectored interrupt requires the ISR to poll all devices.
• (B) A non-maskable interrupt cannot be disabled by the mask register.
• (C) A higher-priority interrupt may interrupt a lower-priority ISR when nesting is allowed.
• (D) In a daisy chain, the device nearest the CPU has the highest priority.

DAnswer Vault