Phase 4 Checkpoint: 15 questions across the memory hierarchy.
⏱️
15 questions · 25 marks · 45 minutes. Negative marking on MCQ only: −1/3 mark for a wrong 1-mark MCQ, −2/3 for a wrong 2-mark MCQ. No negative marking for MSQ or NAT; MSQ has no partial credit.
Q1NAT1 markHit ratio
A cold cache with 32-byte blocks; a loop reads 1,024 consecutive 2-byte shorts (aligned). Misses?
Numerical answer: ________
Q2NAT2 marksAMAT
Simultaneous access: t_c = 2 ns, t_m = 70 ns, h = 0.97. Average (ns)?
Numerical answer: ________
Q3NAT2 marksRefresh
A DRAM with 2,048 rows; each row refreshed every 16 ms; 80 ns per row. Refresh overhead (percent)?
Numerical answer: ________
Q4NAT1 markChips
How many 1K × 8 chips for a 16 KB byte-addressable memory?
Numerical answer: ________
Q5MCQ1 markDecoder
A 64 KB byte-addressable memory from 8K × 8 chips needs which row-select decoder?
- (A) 13-to-8192
- (B) 2-to-4
- (C) 4-to-16
- (D) 3-to-8
Q6NAT2 marksDisk
Seek 6 ms; 12,000 rpm; 250 sectors per track. Average time to read one sector (ms)?
Numerical answer: ________
Q7NAT1 markDirect split
32-bit addresses, 8 KB direct-mapped, 32-byte blocks. Tag bits?
Numerical answer: ________
Q8NAT2 marksSet split
32-bit addresses, 1 MB 16-way cache, 64-byte blocks. Tag bits?
Numerical answer: ________
Q9NAT2 marksDirectory
8-way, 64 KB, 32-byte blocks, 32-bit addresses; V, D and 3 LRU bits per line. Directory bits?
Numerical answer: ________
Q10NAT2 marksTrace
A 4-line 2-way set-associative LRU cache: blocks 0, 2, 4, 0, 6, 2, 4, 1, 3, 1. Misses?
Numerical answer: ________
Q11NAT2 marksReplacement
A 3-line fully associative cache, FIFO: blocks 1, 2, 3, 1, 4, 1, 5, 2. Misses?
Numerical answer: ________
Q12NAT2 marksWrite-back
t_c = 1 ns; block 100 ns; h = 0.98; 40% dirty victims. AMAT (ns)?
Numerical answer: ________
Q13NAT2 marksCPI
Base CPI 1; 1.25 accesses per instruction; miss rate 4%; penalty 60 cycles. Effective CPI?
Numerical answer: ________
Q14NAT2 marksTwo levels
L1: 1 cycle, 5% miss; L2: 20 cycles, local miss 10%; memory 200 cycles. AMAT (cycles)?
Numerical answer: ________
Q15NAT1 markArrays
Row-wise pass over short S[100][64] (2 bytes each, aligned at 0) with 64-byte blocks, cold cache. Misses?
Numerical answer: ________
✓Answer Vault
Answer Vault
Try the questions first. Open when you are ready to check.
Q1 Answer: 641 mark
16 shorts per block.
Re-read: Lesson 4.1.1 — Why a hierarchy: speed, cost, size; locality; hit, miss, hit ratio
Q2 Answer: 4.042 marks
0.97 × 2 + 0.03 × 70 = 1.94 + 2.1.
Re-read: Lesson 4.1.2 — Average memory access time: hierarchical vs simultaneous access; multi-level formulas
Q3 Answer: 1.0242 marks
2048 × 80 ns = 163.84 µs; / 16 ms.
Re-read: Lesson 4.1.3 — Memory chips: SRAM vs DRAM, ROM types, DRAM refresh; chip organisation 2ᵏ × n
Q4 Answer: 161 mark
16K/1K × 8/8.
Re-read: Lesson 4.1.4 — Memory interfacing: building larger memories from chips, address decoding, chip counts
Q5 Answer: (D)1 mark
8 rows.
- (A) is wrong: That is the chip's internal decoding.
- (B) is wrong: Only 4 rows.
- (C) is wrong: 16 rows.
Re-read: Lesson 4.1.4 — Memory interfacing: building larger memories from chips, address decoding, chip counts
Q6 Answer: 8.522 marks
Latency 2.5; transfer 5/250 = 0.02; 6 + 2.5 + 0.02.
Re-read: Lesson 4.1.5 — Secondary storage and bandwidth: disk access time, transfer rate, interleaved memory
Q7 Answer: 191 mark
Offset 5, lines 256 → 8; 32 − 13.
Re-read: Lesson 4.2.1 — Cache lines and blocks; direct mapping: tag, line, offset
Q8 Answer: 162 marks
Lines 16,384; sets 1,024 → 10; offset 6; tag 16.
Re-read: Lesson 4.2.2 — Fully associative and set-associative mapping; comparators and multiplexers
Q9 Answer: 491522 marks
Lines 2048; sets 256 → 8 bits; offset 5; tag 19; per line 19 + 1 + 1 + 3 = 24 → 2048 × 24 = 49,152.
Re-read: Lesson 4.2.3 — Tag directory size and cache hardware: valid, dirty and replacement bits
Q10 Answer: 92 marks
2 sets. Set 0 gets 0, 2, 4, 0, 6, 2, 4 (all even): with 2 ways and LRU each one misses (7). Set 1 gets 1 M, 3 M, 1 H. Total 9.
Re-read: Lesson 4.2.4 — Tracing references: hits and misses; compulsory, capacity and conflict misses
Q11 Answer: 72 marks
1, 2, 3 M; 1 H (FIFO order unchanged); 4 M (evicts 1); 1 M (evicts 2); 5 M (evicts 3); 2 M (evicts 4). Misses: 7.
Re-read: Lesson 4.2.5 — Replacement policies: LRU, FIFO, random, optimal; tracing sets
Q12 Answer: 3.82 marks
1 + 0.02 × 140 = 3.8.
Re-read: Lesson 4.3.1 — Write policies: write-through vs write-back, dirty bit, write-allocate
Q13 Answer: 42 marks
1 + 1.25 × 0.04 × 60 = 4.
Re-read: Lesson 4.3.2 — Miss penalty and block transfer; memory-stall cycles; CPI with cache misses
Q14 Answer: 32 marks
1 + 0.05 × (20 + 20) = 3.
Re-read: Lesson 4.3.3 — Multilevel caches: L1 and L2, local vs global miss rate, inclusion
Q15 Answer: 2001 mark
12,800 bytes / 64.
Re-read: Lesson 4.3.4 — Programs and caches: array layout, loop order, counting misses