Datapath

ACompressed recap

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Registers: PC (next address), IR (current instruction), MAR (address bus), MDR (data bus), GPRs, SP, flags, invisible temporaries. RTL: ← transfers, commas for the same step. Single bus: one out per step, MAR in-only, ALU A from MUX(Y, 4), B from the bus, result in Z. Fetch 3 steps; register ALU execute 3; ALU with a memory operand 4; PC-relative branch 2. Two buses: register op execute 2 steps; three buses: 1 step. Count steps with: one value per bus per step, one ALU op per step, values written are readable next step.

BMerged rule card

2.2.1 CPU registers and register transfer notation: PC, IR, MAR, MDR, GPRs, flags, SP

• PC: next instruction address. IR: current instruction. MAR: address bus. MDR: data bus.
• Memory read: MAR ← addr; MDR ← M[MAR] (Read, wait MFC). Write: MAR, MDR set; M[MAR] ← MDR.
• RTL: ← transfer; commas = same step; IR(address) = address field.
• Fetch: MAR ← PC; MDR ← M[MAR], PC ← PC + 4; IR ← MDR.

2.2.2 Single-bus datapath: control signals and micro-operation steps for fetch and execute

• Single bus: one out per step; MAR in-only; ALU A ← MUX(Y, 4), B ← bus; result → Z.
• Fetch: PCout, MARin, Read, Select4, Add, Zin | Zout, PCin, Yin, WMFC | MDRout, IRin (3 steps).
• Register ALU op execute: 3 steps (Y ← src1; Z ← Y op src2; dest ← Z).
• Memory operand: + MAR load / Read step; overlap work with WMFC.
• Branch: offset + Y (PC) → Z → PC: 2 steps.

2.2.3 Two- and three-bus datapaths; counting cycles per instruction

• Three-bus: R1 ← R2 + R3 in 1 step; two-bus: 2 steps; single bus: 3 steps.
• Counting: one value per bus per step; one ALU op per step; written values readable next step.
• Memory reads need an address step and a data step (or WMFC).
• The question's datapath description always wins.

CInterleaved GATE-style questions

Q1MCQ1 markRegister roles

During the third fetch step on the single bus (MDRout, IRin), which register receives the instruction?

• (A) IR
• (B) Y
• (C) MAR
• (D) PC

Q2NAT1 markMAR width

A CPU has a 4 GB byte-addressable address space. How many bits is the MAR?

Numerical answer: ________

Q3NAT2 marksSingle-bus count

Total single-bus control steps (fetch included) for ADD R1, R2, R3 followed by ADD R4, (R5)?

Numerical answer: ________

Q4MSQ2 marksFetch signals

In single-bus fetch step 1, which signals are active?

• (A) IRin
• (B) Select4
• (C) MARin
• (D) PCout

Q5NAT2 marksBranch steps

On the single bus, total steps (fetch included) for a taken PC-relative branch?

Numerical answer: ________

Q6NAT1 markNot-taken branch

On the single bus, total steps (fetch included) for a conditional branch whose condition is false, if the check happens in step 4 with End?

Numerical answer: ________

Q7NAT2 marksThree-bus program

On the three-bus datapath (fetch 3 steps), how many steps for 50 register–register ALU instructions?

Numerical answer: ________

Q8MCQ1 markOverlap

In ADD R1, (R3), step 5 is "R1out, Yin, WMFC". What is gained by putting R1out, Yin here?

• (A) It updates the flags
• (B) It does useful work while waiting for memory, saving a step
• (C) Nothing; it could go anywhere
• (D) It is required before MARin

DAnswer Vault