Memory interfacing: building larger memories from chips, address decoding, chip counts

0 · Recall Warm-up

Answer from memory first. Answers are in the Answer Vault at the bottom.

• Address and data lines of a 64K × 16 chip? from Lesson 4.1.3
• Three-level hierarchical AMAT formula? from Lesson 4.1.2
• What does a k-to-2ᵏ decoder with enable do? from Lesson 0.2.3

1 · The Hook

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Memory chips come in fixed shapes, like 2K × 8. A computer wants, say, 16 KB with 16-bit words. You build it the way you tile a floor: chips side by side for a wider word, rows of chips for more words, and a decoder that picks the row. GATE asks how many chips, how many address lines, and which addresses each chip answers.

2 · Predict First

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You need a 2K × 16 memory but have only 2K × 8 chips. How many chips, and how are they connected?

Make a guess in your head. The answer opens Section 3.

3 · Core Concept

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Predict First — the answer

2 chips side by side: both get the same 11 address lines and the same chip select; one supplies data bits 15–8, the other bits 7–0.

Width (word) expansion

To make wider words, put B/b chips side by side. All share the address lines and chip select; each provides b of the B data bits.

Depth (capacity) expansion

To make more words, use W/w rows of chips. The low log₂ w address bits go to every chip; the high log₂(W/w) address bits go to a decoder whose outputs drive the chip-select inputs of the rows. Exactly one row is enabled per access.

General recipe: W × B memory from w × b chips

• Chips = (W / w) × (B / b).
• Total address lines = log₂ W.
• Lines to every chip = log₂ w.
• Decoder: log₂(W/w) inputs → W/w outputs.

Example: 16 KB byte-addressable from 2K × 8 chips

• Chips: (16K / 2K) × (8 / 8) = 8.
• Address lines: log₂ 16K = 14 (A13–A0).
• A10–A0 (11 lines) to every chip; A13–A11 (3 lines) into a 3-to-8 decoder.
• Row j answers addresses j × 2K to (j + 1) × 2K − 1: row 0 is 0x0000–0x07FF, row 5 is 0x2800–0x2FFF.

Address map from a decoder condition

In a 64 KB space (A15–A0), a chip enabled when A15 A14 A13 = 101 answers every address of the form 101x xxxx xxxx xxxx: 0xA000 to 0xBFFF (8 KB).

Partial decoding

If some high address bits are ignored by the decoder, a chip answers at several addresses (aliasing / fold-back): cheaper logic, wasted address space.

4 · Visual

Depth expansion: low address bits to every chip, high bits to a decoder that selects one row.

5 · Worked Examples

Example 1 Easy

How many 1K × 4 chips make a 4K × 8 memory?

Solution

(4K/1K) × (8/4) = 4 × 2 = 8.

Example 2 Medium

A 2048 × 16 memory (word-addressable) is built from 128 × 8 chips. How many chips, total address lines, lines common to all chips, and what decoder?

Solution

Chips (2048/128) × (16/8) = 16 × 2 = 32. Address lines log₂ 2048 = 11; common log₂ 128 = 7; decoder 4-to-16 (11 − 7 = 4 bits).

Example 3 GATE

In a 64 KB address space, a 16 KB memory chip is enabled when A15 = 0 and A14 = 1. Which address range does it occupy?

Solution

01xx xxxx xxxx xxxx → 0x4000 to 0x7FFF.

6 · GATE Traps

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• Width expansion chips share address and CS; depth expansion rows have separate CS from the decoder.
• Total chips multiply the two factors.
• The decoder takes the high bits; the chips take the low bits.
• Count address lines from the number of words, not bytes, for a word-addressable memory.

7 · Memory Hook

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"Side by side for width, rows for depth, decoder on the top bits."

8 · Connect the Dots

You can now assemble main memory from chips and read its address map. The last lesson of Chapter 4.1 goes one level down the hierarchy, to disks, and one level sideways, to interleaved memory that delivers blocks faster.

9 · Self-Test

GATE format. Try every question before opening the vault.

Q1NAT1 markChip count

How many 256 × 4 chips are needed for a 4K × 16 memory?

Numerical answer: ________

Q2NAT2 marksDecoder

A 32 KB byte-addressable memory is built from 4K × 8 chips. How many inputs does the row-select decoder have?

Numerical answer: ________

Q3NAT2 marksCommon lines

Same memory (32 KB from 4K × 8 chips): how many address lines go to every chip?

Numerical answer: ________

Q4MCQ2 marksAddress range

In a 64 KB space, a chip is enabled when A15 A14 A13 A12 = 1100. Its address range is:

• (A) 0xB000 – 0xBFFF
• (B) 0xC000 – 0xCFFF
• (C) 0xC000 – 0xDFFF
• (D) 0x0C00 – 0x0CFF

Q5NAT1 markWidth expansion

How many 64K × 1 chips form a 64K × 32 memory?

Numerical answer: ________

10 · Rule Card

• Chips = (W/w)(B/b). Address lines = log₂ W; common = log₂ w; decoder log₂(W/w) → W/w.
• Width expansion: shared address and CS; depth expansion: decoder on high bits drives CS.
• Address range: fixed high bits, all combinations of the low bits.
• Partial decoding → aliasing.

11 · Concept Ledger

Unlocked in this lesson. From here on, these terms may be used.

width (word) expansiondepth (capacity) expansionchip-select decoderaddress mapchip-count formulapartial decoding and aliasing

12 · Answer Vault