Control signals, control steps and the step counter: what a control unit must produce

0 · Recall Warm-up

Answer from memory first. Answers are in the Answer Vault at the bottom.

• Single bus: list the 3 fetch steps. from Lesson 2.2.2
• Three-bus execute steps for R1 ← R2 + R3? from Lesson 2.2.3
• What does a k-to-2ᵏ decoder do? from Lesson 0.2.3

1 · The Hook

🎣

Phase 2 listed, for every step, which signals must be 1: PCout, MARin, Read and so on. Someone has to produce those 1s at exactly the right step, for every instruction, every cycle. That someone is the control unit. This lesson defines precisely what it must produce and from what inputs.

2 · Predict First

🤔

The control unit decides that in step 5 of ADD R1, R2, R3 the signals R3out, SelectY, Add and Zin must be 1. What information does it need to make that decision?

Make a guess in your head. The answer opens Section 3.

3 · Core Concept

💡

Predict First — the answer

Which instruction is running (the opcode in IR), which step it is in (a step counter), and for branches the flags. Also memory's MFC signal, to know when it may move past a WMFC step.

What the control unit does

In every clock step it outputs the full set of control signals: one bit per signal (Rin, Rout for each register, Read, Write, ALU function, Select4/SelectY, WMFC, End …). Phase 2's step tables are its specification.

Its inputs

• IR (the opcode, sometimes addressing-mode bits),
• a step counter that counts the steps of the current instruction,
• condition codes (flags Z, N, C, V) for conditional instructions,
• external signals: MFC from memory, interrupt requests (Phase 6).

The step counter

• A counter of ⌈log₂(max steps)⌉ bits, decoded into timing signals T1, T2, … Tn: exactly one is 1 at a time.
• It advances by one each clock cycle.
• End resets it to T1 (the next instruction's fetch).
• WMFC freezes it: the counter is not enabled until MFC arrives, so the step repeats until memory is done.

Steps per instruction vary (6 for a register add, 7 for ADD R1, (R3) on the single bus), so instruction time = (number of steps, including any waiting) × clock period.

Counting control signals

A single-bus CPU with n general-purpose registers has Rin and Rout for each of them, plus signals for PC, MAR, MDR, IR, Y, Z, memory, ALU function and sequencing. The total, often 40 to 100+ signals, matters for microinstruction width (Chapter 3.2).

Example (single bus, R0–R7):

Two ways to build it

• Hardwired (Lesson 3.1.2): logic gates compute each signal from IR, step and flags.
• Microprogrammed (Chapter 3.2): the signals of each step are stored as a word in a small memory and read out step by step.

4 · Visual

The control unit maps (instruction, step, conditions) to the signals of that step.

5 · Worked Examples

Example 1 Easy

The longest instruction needs 11 steps. How many bits does the step counter need?

Solution

⌈log₂ 11⌉ = 4.

Example 2 Medium

A single-bus CPU runs at 500 MHz. An instruction takes 7 steps, and its WMFC step waits 2 extra cycles for memory. How long does it take?

Solution

7 + 2 = 9 cycles × 2 ns = 18 ns.

Example 3 GATE

A single-bus CPU has 16 general-purpose registers, each with Rin and Rout. The other signals are the same 20 as in the lesson's table (36 − 16). How many control signals in total?

Solution

16 × 2 + 20 = 52.

6 · GATE Traps

⚠️

• WMFC freezes the step counter; it does not skip a step.
• End resets the counter to T1; it does not stop the processor.
• Timing signals T1…Tn are one-hot (decoded counter).
• The control unit needs the flags only for conditional behaviour.

7 · Memory Hook

🧠

"What instruction, which step, any conditions?" The control unit's three questions every cycle.

8 · Connect the Dots

Phase 2 gave the step tables; this lesson defined the machine that plays them back. Next: the hardwired way, where each control signal is a logic equation over (instruction, step, flags).

9 · Self-Test

GATE format. Try every question before opening the vault.

Q1NAT1 markCounter bits

The longest instruction of a CPU needs 18 control steps. Minimum step-counter width?

Numerical answer: ________

Q2NAT2 marksInstruction time

A 1 GHz single-bus CPU: an instruction needs 8 steps, and memory makes its two WMFC steps wait 3 extra cycles each. Execution time in ns?

Numerical answer: ________

Q3MCQ1 markInputs

Which is NOT an input to the control unit?

• (A) The step counter's timing signals
• (B) The condition flags
• (C) The opcode in IR
• (D) The contents of general-purpose register R3

Q4NAT2 marksSignal count

A single-bus CPU has 32 GPRs (each with Rin and Rout) and 25 other control signals. Total control signals?

Numerical answer: ________

Q5MSQ2 marksStep counter

Which statements are true?

• (A) End advances the counter to the next step of the same instruction.
• (B) WMFC holds the counter until memory signals completion.
• (C) The step counter's outputs are decoded into one-hot timing signals.
• (D) Different instructions may need different numbers of steps.

10 · Rule Card

• Control unit inputs: IR opcode, step counter (T1…Tn), flags, MFC/interrupts. Output: all control signals per step.
• Step counter: ⌈log₂ max steps⌉ bits, decoded one-hot; End resets; WMFC freezes.
• Instruction time = (steps + waits) × clock period.
• Control signals ≈ 2 per register (in/out) + memory + ALU + MUX + sequencing.

11 · Concept Ledger

Unlocked in this lesson. From here on, these terms may be used.

control unitcontrol signalstep countertiming signals T1…TnEndWMFC freezehardwired vs microprogrammed (preview)

12 · Answer Vault