5.3.2 Pipeline performance from an instruction mix: effective CPI, comparing designs

0 · Recall Warm-up

Answer from memory first. Answers are in the Answer Vault at the bottom.

Timing rule for starting stage s? from Lesson 5.3.1
Predict-not-taken CPI? from Lesson 5.2.4
CPU time formula? from Lesson 0.1.2

1 · The Hook

🎣

Deeper pipelines allow faster clocks but pay more per branch and per load. Is an 8-stage, 1.6 GHz design better than a 5-stage, 1 GHz one? Only the performance equation can say. GATE asks this as "which processor is faster, and by how much".

2 · Predict First

🤔

Design A: CPI 1.34 at 1 GHz. Design B: CPI 1.68 at 1.6 GHz. Same program, same instruction count. Which is faster?

Make a guess in your head. The answer opens Section 3.

3 · Core Concept

💡

Predict First — the answer

Time per instruction: A = 1.34 × 1 ns = 1.34 ns; B = 1.68 × 0.625 ns = 1.05 ns. B is faster, by 1.34 / 1.05 ≈ 1.28.

CPI from a mix

CPI = 1 + Σ (fraction of instructions with a hazard × stall cycles for it).

Design A (5 stages, 1 GHz): branch penalty 2, load-use stall 1. Mix: 20% branches (60% taken, predict-not-taken), 25% loads, 40% of loads followed by a dependent instruction. CPI_A = 1 + 0.2 × 0.6 × 2 + 0.25 × 0.4 × 1 = 1 + 0.24 + 0.1 = 1.34.

Design B (8 stages, 1.6 GHz): branch penalty 4, load-use stall 2, same mix. CPI_B = 1 + 0.2 × 0.6 × 4 + 0.25 × 0.4 × 2 = 1 + 0.48 + 0.2 = 1.68.

Time and MIPS

Time per instruction = CPI × τ. A: 1.34 ns; B: 1.68 × 0.625 = 1.05 ns.
MIPS = f / CPI. A: 1000 / 1.34 ≈ 746; B: 1600 / 1.68 ≈ 952.
Speedup of B over A = 1.34 / 1.05 ≈ 1.28.

Pipelined vs non-pipelined with stalls

Speedup = (CPI_np × τ_np) / (CPI_p × τ_p). A non-pipelined machine with a 5 ns instruction time vs a 5-stage pipeline with τ = 1.1 ns (latches) and CPI 1.34: 5 / (1.34 × 1.1) ≈ 3.39.

Memory stalls too

Cache misses (Lesson 4.3.2) add to the same CPI: CPI = 1 + hazard stalls + memory-stall cycles per instruction.

4 · Visual

	Design A	Design B
Stages	5	8
Clock	1 GHz (1 ns)	1.6 GHz (0.625 ns)
Branch penalty	2	4
Load-use stall	1	2
CPI	1.34	1.68
Time per instruction	1.34 ns	1.05 ns

5 · Worked Examples

Example 1 Easy

CPI 1.5 at 2 GHz. Time per instruction and MIPS?

Solution

0.75 ns; 1,333 MIPS (2000 / 1.5).

Example 2 Medium

Same mix as Design A, but the branch is resolved in ID (penalty 1). CPI?

Solution

1 + 0.2 × 0.6 × 1 + 0.1 = 1.22.

Example 3 GATE

P1: 5-stage pipeline, stage delays 1, 2, 2, 1, 1 ns (no latch delay). P2: 4-stage pipeline, stage delays 1, 1.5, 1.5, 1.5 ns. Ignoring hazards, what is the ratio of P2's peak clock frequency to P1's?

Solution

P1 τ = 2 ns (500 MHz); P2 τ = 1.5 ns (≈ 667 MHz). Ratio = 2 / 1.5 ≈ 1.33.

6 · GATE Traps

⚠️

Compare time per instruction (CPI × τ), never CPI alone or clock alone.
Stall terms multiply fraction × probability × penalty.
A deeper pipeline usually has larger penalties.
Peak clock = 1 / (slowest stage + latch).

7 · Memory Hook

🧠

"CPI times cycle, then compare."

8 · Connect the Dots

Phase 5 is complete: pipeline timing, hazards and their costs, full cycle counts and design comparison. Phase 6 turns to I/O: how the CPU talks to devices, and how interrupts and DMA let it avoid waiting for them.

9 · Self-Test

GATE format. Try every question before opening the vault.

Q1NAT2 marksMix CPI

5-stage pipeline: 25% branches, all stall 2 cycles; 30% loads, a third of them followed by a dependent instruction (1 stall). CPI?

Numerical answer: ________

Q2NAT2 marksCompare

Processor X: CPI 1.2 at 1.5 GHz. Processor Y: CPI 1.8 at 2.4 GHz. How many times faster is Y than X (2 decimals)?

Numerical answer: ________

Q3NAT1 markMIPS

CPI 1.25 at 2.5 GHz. MIPS?

Numerical answer: ________

Q4NAT2 marksPeak clock ratio

P1: stages 2, 3, 2, 2 ns. P2: stages 1, 1.5, 1.5, 1, 1.5 ns. No latch delay. Ratio of P2's peak clock frequency to P1's?

Numerical answer: ________

Q5MCQ1 markDeeper pipelines

Making a pipeline deeper (more, shorter stages) typically:

(A) raises the clock rate and the branch penalty
(B) removes data hazards
(C) leaves CPI unchanged
(D) lowers the clock rate and the branch penalty

10 · Rule Card

CPI = 1 + Σ fraction × (probability) × stall cycles (+ memory stalls).
Time per instruction = CPI × τ; MIPS = f / CPI.
Speedup = (CPI·τ)_old / (CPI·τ)_new.
Deeper pipeline: faster clock, bigger penalties.

11 · Concept Ledger

Unlocked in this lesson. From here on, these terms may be used.

CPI from an instruction mixtime per instructionMIPS of a pipelinedesign comparisonpeak clock frequencydeeper-pipeline trade-off

12 · Answer Vault

Answer Vault

Try the questions first. Open when you are ready to check.

Recall Warm-up

max(end of own s−1, end of previous instruction's s, operand ready, branch resolved) + adjustments.
1 + f_b × p_taken × penalty.
IC × CPI × T.