ACompressed recap
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Timing rule: start(i, s) = max(end(i, s−1) + 1, end(i−1, s) + 1, operand ready, branch resolved + 1); multi-cycle stages block later instructions; forward at the end of EX (ALU) or MEM (load). CPI = 1 + Σ fraction × probability × stalls; time per instruction = CPI × τ; compare designs by CPI × τ; MIPS = f/CPI; peak clock = 1/(max stage + latch).
BMerged rule card
5.3.1 Full cycle counting: mixed hazards and multi-cycle stages
- start(i,s) = max(end(i,s−1)+1, end(i−1,s)+1, operand ready, branch resolved+1); end = start + cycles − 1.
- Multi-cycle EX blocks later EX; forward at its end.
- Answer = end of last stage of the last instruction.
- Out-of-order completion creates WAR/WAW hazards.
5.3.2 Pipeline performance from an instruction mix: effective CPI, comparing designs
- CPI = 1 + Σ fraction × (probability) × stall cycles (+ memory stalls).
- Time per instruction = CPI × τ; MIPS = f / CPI.
- Speedup = (CPI·τ)_old / (CPI·τ)_new.
- Deeper pipeline: faster clock, bigger penalties.
CInterleaved GATE-style questions
Q1NAT2 marksTable
| S1 | S2 | S3 | |
|---|---|---|---|
| I1 | 1 | 2 | 1 |
| I2 | 2 | 1 | 2 |
| I3 | 1 | 1 | 1 |
Cycles for I1, I2, I3 once?
Numerical answer: ________
Q2NAT2 marksMulti-cycle
With forwarding, DIV takes 4 cycles in EX: DIV R1, R2, R3 · ADD R4, R1, R1 · ADD R5, R6, R7. Cycles?
Numerical answer: ________
Q3NAT2 marksCPI
20% branches with 70% taken (predict-not-taken, penalty 3); 20% loads with half followed by a use (1 stall). CPI?
Numerical answer: ________
Q4NAT2 marksCompare
A: CPI 1.4 at 1 GHz. B: CPI 2.0 at 1.6 GHz. Time per instruction of the faster one (ns)?
Numerical answer: ________
Q5MCQ1 markRule
In the timing rule, why can I2 not start S2 before I1 has finished S2?
- (A) The stage hardware is busy (in-order use of each stage)
- (B) Cache miss
- (C) Branch hazard
- (D) Data hazard
Q6NAT1 markMIPS
CPI 1.6 at 800 MHz. MIPS?
Numerical answer: ________
DAnswer Vault
Answer Vault
Try the questions first. Open when you are ready to check.
Q1 Answer: 72 marks
I1: S1 1, S2 2–3, S3 4. I2: S1 2–3, S2 4, S3 5–6. I3: S1 4, S2 5, S3 7 (waits for I2 to finish S3 in cycle 6). Total 7.
Re-read: Lesson 5.3.1 — Full cycle counting: mixed hazards and multi-cycle stages
Q2 Answer: 102 marks
I1 EX 3–6, MEM 7, WB 8; I2 EX 7, MEM 8, WB 9; I3 EX 8, MEM 9, WB 10.
Re-read: Lesson 5.3.1 — Full cycle counting: mixed hazards and multi-cycle stages
Q3 Answer: 1.522 marks
1 + 0.42 + 0.1.
Re-read: Lesson 5.3.2 — Pipeline performance from an instruction mix: effective CPI, comparing designs
Q4 Answer: 1.252 marks
A 1.4 ns; B 2.0 × 0.625 = 1.25 ns.
Re-read: Lesson 5.3.2 — Pipeline performance from an instruction mix: effective CPI, comparing designs
Q5 Answer: (A)1 mark
Each stage serves one instruction at a time.
- (B) is wrong: Not about memory.
- (C) is wrong: No branch.
- (D) is wrong: Not about values.
Re-read: Lesson 5.3.1 — Full cycle counting: mixed hazards and multi-cycle stages
Q6 Answer: 5001 mark
800 / 1.6.
Re-read: Lesson 5.3.2 — Pipeline performance from an instruction mix: effective CPI, comparing designs