Pipeline basics

ACompressed recap

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k stages, pipeline registers between them, τ = max stage delay + latch delay. n instructions: (k + n − 1)τ pipelined vs n × Σ delays non-pipelined. Speedup → k for balanced stages; → Σtᵢ/(max tᵢ + d) in general; efficiency = speedup/k; throughput → 1/τ. Splitting the bottleneck lowers τ but adds a stage. 5-stage RISC: IF (fetch), ID (read registers), EX (ALU/address/branch), MEM (load/store), WB (write register); split-cycle register file; separate caches; ideal CPI 1.

BMerged rule card

5.1.1 The pipeline idea: stages, latches, cycle time, k + n − 1 cycles

• Pipeline: k stages, pipeline registers between them; all move each cycle.
• τ = max stage delay + latch delay.
• Pipelined time = (k + n − 1)τ; non-pipelined = n × Σ stage delays.
• Space–time diagram: instructions × cycles.

5.1.2 Speedup, efficiency, throughput; unequal stages, latch delay, splitting stages

• Speedup = T_nonpipe / T_pipe; balanced: nk/(k+n−1) → k.
• Unequal: large-n speedup = Σtᵢ / (max tᵢ + d).
• Efficiency = speedup/k = n/(k+n−1) (balanced). Throughput → 1/τ.
• Splitting the bottleneck: new τ = new max + d, k + 1 stages.

5.1.3 The 5-stage RISC pipeline IF ID EX MEM WB; space–time diagrams

• IF: fetch, PC + 4. ID: decode, read registers. EX: ALU / address / branch. MEM: load/store. WB: write register.
• Separate I- and D-caches; register file write first half, read second half.
• Instruction i (no stalls) is in stage s at cycle i + s − 1.
• Ideal CPI = 1.

CInterleaved GATE-style questions

Q1NAT1 markCycles

A 6-stage pipeline runs 45 instructions. Cycles?

Numerical answer: ________

Q2NAT2 marksTime

Stages 8, 10, 7, 9, 6 ns; latch 1 ns. Time for 20 instructions (ns)?

Numerical answer: ________

Q3NAT2 marksSpeedup

The same pipeline: large-n speedup over non-pipelined (2 decimals)?

Numerical answer: ________

Q4NAT2 marksSplit

Stages 30, 50, 40 ns, latch 2 ns. Splitting the 50 ns stage into 25 + 25, what is the new cycle time (ns)?

Numerical answer: ________

Q5NAT1 markEfficiency

Balanced 5-stage pipeline, 45 instructions. Efficiency?

Numerical answer: ________

Q6MCQ1 markStage role

Which stage writes the result of ADD R1, R2, R3 into R1?

• (A) EX
• (B) MEM
• (C) WB
• (D) ID

Q7MSQ2 marksConventions

Which conventions of the 5-stage pipeline are assumed in these notes unless a question says otherwise?

• (A) Branches are resolved in EX
• (B) Every instruction uses the MEM stage for real work
• (C) Register file written in the first half of a cycle, read in the second half
• (D) Separate instruction and data caches

Q8NAT1 markThroughput

A pipeline with τ = 2 ns runs a very long program. Throughput in instructions per ns?

Numerical answer: ________

DAnswer Vault