Phase 2 Checkpoint: 15 questions on ALU design, adders, multiplication and datapaths.
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15 questions · 22 marks · 40 minutes. Negative marking on MCQ only: −1/3 mark for a wrong 1-mark MCQ, −2/3 for a wrong 2-mark MCQ. No negative marking for MSQ or NAT; MSQ has no partial credit.
Q1NAT1 markALU control
An ALU with 16 encoded operations needs how many select bits?
Numerical answer: ________
Q2MCQ1 markSubtractor
An adder computes a + NOT b with carry-in 0. The result equals:
- (A) a − b
- (B) a − b − 1
- (C) a + b
- (D) b − a
Q3NAT2 marksOverflow bit
8-bit addition 1000 0000 + 1111 1111 (−128 + −1). What is V (0 or 1)?
Numerical answer: ________
Q4NAT1 markRipple carry
A 64-bit ripple-carry adder with carry delay 2 gate delays per bit. Gate delays until c₆₄?
Numerical answer: ________
Q5NAT2 marksRipple sum
A 16-bit ripple-carry adder: t_c = 4 ns, t_s = 5 ns. Last sum bit ready at (ns)?
Numerical answer: ________
Q6MCQ1 markCLA
In a carry-lookahead adder, c₂ equals:
- (A) g₁ + p₁g₀ + p₁p₀c₀
- (B) g₁p₁ + g₀p₀ + c₀
- (C) g₁ + g₀ + c₀
- (D) p₁ + g₁g₀ + c₀
Q7NAT2 marksBlock CLA
A 64-bit adder of sixteen 4-bit CLA blocks rippled together: g/p 1 gate delay, 2 gate delays per block for the carry-out. When is c₆₄ ready (gate delays)?
Numerical answer: ________
Q8NAT2 marksBooth
Additions plus subtractions in Booth's algorithm for the 7-bit multiplier 0101101?
Numerical answer: ________
Q9NAT1 markShift-and-add
Unsigned multiplier 1111 0000: how many additions in shift-and-add?
Numerical answer: ________
Q10NAT1 markBooth on runs
Booth operations (adds + subtracts) for the 8-bit multiplier 1111 0000?
Numerical answer: ________
Q11MCQ1 markMDR
Which register receives data from memory during a read?
- (A) PC
- (B) MDR
- (C) IR
- (D) MAR
Q12NAT2 marksSingle-bus steps
Total single-bus steps (fetch included) for LOAD R1, (R2) (with one WMFC step that does nothing else) plus ADD R1, R1, R3?
Numerical answer: ________
Q13MSQ2 marksSingle-bus rules
Which are true for the single-bus datapath?
- (A) MAR only receives from the bus.
- (B) Fetch takes 3 steps.
- (C) Two registers may receive the same bus value in one step.
- (D) The ALU result can be written directly into R1 in the step it is computed.
Q14NAT2 marksThree-bus
A three-bus CPU (fetch 3 steps, register ALU execute 1 step) and a single-bus CPU (fetch 3, execute 3) both run 2,000 register–register ALU instructions. Ratio of single-bus steps to three-bus steps?
Numerical answer: ________
Q15NAT1 markTwo-bus
In the two-bus model, execute steps for ADD R1, R2, R3?
Numerical answer: ________
✓Answer Vault
Answer Vault
Try the questions first. Open when you are ready to check.
Q1 Answer: 41 mark
log₂ 16.
Re-read: Lesson 2.1.1 — Building an ALU: 1-bit slice, n-bit ALU, subtraction, flags Z N C V
Q2 Answer: (B)1 mark
NOT b = −b − 1, so a + NOT b = a − b − 1.
- (A) is wrong: Needs carry-in 1.
- (C) is wrong: b is inverted.
- (D) is wrong: Wrong order.
Re-read: Lesson 2.1.1 — Building an ALU: 1-bit slice, n-bit ALU, subtraction, flags Z N C V
Q3 Answer: 12 marks
Result 0111 1111 (+127): negative + negative gave positive; c₇ = 0, c₈ = 1 → V = 1.
Re-read: Lesson 2.1.1 — Building an ALU: 1-bit slice, n-bit ALU, subtraction, flags Z N C V
Q4 Answer: 1281 mark
64 × 2.
Re-read: Lesson 2.1.2 — Adder speed: ripple-carry delay, carry-lookahead (generate, propagate), gate-delay counting
Q5 Answer: 652 marks
15 × 4 + 5.
Re-read: Lesson 2.1.2 — Adder speed: ripple-carry delay, carry-lookahead (generate, propagate), gate-delay counting
Q6 Answer: (A)1 mark
Unroll c₂ = g₁ + p₁c₁ with c₁ = g₀ + p₀c₀.
- (B) is wrong: Wrong structure.
- (C) is wrong: Ignores propagation.
- (D) is wrong: Swaps g and p roles.
Re-read: Lesson 2.1.2 — Adder speed: ripple-carry delay, carry-lookahead (generate, propagate), gate-delay counting
Q7 Answer: 332 marks
1 + 16 × 2.
Re-read: Lesson 2.1.2 — Adder speed: ripple-carry delay, carry-lookahead (generate, propagate), gate-delay counting
Q8 Answer: 62 marks
Recoded +1 −1 +1 0 −1 +1 −1: 3 additions, 3 subtractions.
Re-read: Lesson 2.1.3 — Multiplication: shift-and-add, Booth's algorithm; restoring division
Q9 Answer: 41 mark
Four 1 bits.
Re-read: Lesson 2.1.3 — Multiplication: shift-and-add, Booth's algorithm; restoring division
Q10 Answer: 11 mark
Recoded 0 0 0 −1 0 0 0 0: one subtraction (−16).
Re-read: Lesson 2.1.3 — Multiplication: shift-and-add, Booth's algorithm; restoring division
Q11 Answer: (B)1 mark
Data arrives through the data bus into MDR.
- (A) is wrong: Holds the next address.
- (C) is wrong: IR gets it from MDR afterwards.
- (D) is wrong: Address only.
Re-read: Lesson 2.2.1 — CPU registers and register transfer notation: PC, IR, MAR, MDR, GPRs, flags, SP
Q12 Answer: 122 marks
6 + 6.
Re-read: Lesson 2.2.2 — Single-bus datapath: control signals and micro-operation steps for fetch and execute
Q13 Answer: (A) (B) (C)2 marks
The result goes to Z first.
- (D) is wrong: Z must hold the result for one step.
Re-read: Lesson 2.2.2 — Single-bus datapath: control signals and micro-operation steps for fetch and execute
Q14 Answer: 1.52 marks
12,000 / 8,000 = 1.5.
Re-read: Lesson 2.2.3 — Two- and three-bus datapaths; counting cycles per instruction
Q15 Answer: 21 mark
Operands → ALU → Z; Z → R1.
Re-read: Lesson 2.2.3 — Two- and three-bus datapaths; counting cycles per instruction