Phase 1 Checkpoint: 15 questions on instructions, encodings, addressing modes, tracing and subroutines. Memory table: M[200] = 500, M[300] = 400, M[400] = 700, M[500] = 600, M[600] = 900, M[700] = 800, M[800] = 300; R1 = 400, R2 = 200, R3 = 100.
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15 questions · 23 marks · 40 minutes. Negative marking on MCQ only: −1/3 mark for a wrong 1-mark MCQ, −2/3 for a wrong 2-mark MCQ. No negative marking for MSQ or NAT; MSQ has no partial credit.
Q1NAT1 markField widths
A 32-bit instruction: opcode for 100 operations, one register field for 16 registers, and a memory address field taking all remaining bits. Address field width?
Numerical answer: ________
Q2NAT2 marksSigned immediate
A 20-bit instruction has a 5-bit opcode, one register field (32 registers) and a two's-complement immediate. What is the most negative immediate?
Numerical answer: ________
Q3NAT1 markStack code
Number of zero-address instructions (including the final POP) for X = A + B − C × D?
Numerical answer: ________
Q4NAT2 marksExpanding opcode
24-bit instructions with 8-bit address fields. Two-address instructions: 200. One-address instructions: maximum number?
Numerical answer: ________
Q5MCQ1 markFlags
CMP R1, R2 with 8-bit R1 = 0x10 and R2 = 0x10, then BNE L. What happens?
- (A) Branch not taken, because Z = 1
- (B) Branch taken, because Z = 1
- (C) Branch not taken, because C = 0
- (D) Branch taken, because N = 1
Q6NAT1 markIndirect
LOAD R0, @500 loads?
Numerical answer: ________
Q7NAT1 markDisplacement
LOAD R0, 100(R2) loads?
Numerical answer: ________
Q8NAT2 marksPC-relative
A 4-byte branch at address 0x400 (1024) has offset −20. Target address in decimal?
Numerical answer: ________
Q9MCQ1 markAuto-decrement
R1 = 400; LOAD R0, −(R1) with 100-byte operands. Afterwards:
- (A) R0 = 700, R1 = 300
- (B) R0 = 700, R1 = 400
- (C) R0 = 400, R1 = 300
- (D) R0 = 400, R1 = 400
Q10MSQ2 marksModes
Which pairs are matched correctly?
- (A) Pointer in a register — register indirect
- (B) Relocatable branch — PC-relative
- (C) Constant — direct
- (D) Array element A[i] — indexed
Q11NAT2 marksMemory references
Count all memory accesses (one-word instructions): LOAD R1, @A · ADD R1, R1, (R2) · STORE R1, B.
Numerical answer: ________
Q12NAT2 marksTrace
How many instructions execute? MOV R1, #0 · MOV R2, #7 · LOOP: ADD R1, R1, #3 · SUB R2, R2, #1 · BNZ R2, LOOP · STORE R1, X · HALT.
Numerical answer: ________
Q13NAT1 markReturn address
A 2-word CALL on a word-addressable machine is at address 300. Return address?
Numerical answer: ________
Q14NAT2 marksStack
SP = 2000, downward stack, 4-byte pushes. A sequence makes 7 pushes and 3 pops. Final SP?
Numerical answer: ________
Q15MCQ2 marksCycle count
A loop of LOAD (3 cycles), ADD (1), SUB (1), BNZ (2) runs 12 times after 3 one-cycle setup instructions. Total cycles?
- (A) 75
- (B) 84
- (C) 87
- (D) 99
✓Answer Vault
Answer Vault
Try the questions first. Open when you are ready to check.
Q1 Answer: 211 mark
Opcode 7, register 4; 32 − 11 = 21.
Re-read: Lesson 1.1.1 — Instruction = opcode + operands; instruction formats; the instruction cycle
Q2 Answer: -5122 marks
Immediate 20 − 5 − 5 = 10 bits → −2⁹ = −512.
Re-read: Lesson 1.1.1 — Instruction = opcode + operands; instruction formats; the instruction cycle
Q3 Answer: 81 mark
Postfix A B + C D × −: PUSH A, PUSH B, ADD, PUSH C, PUSH D, MUL, SUB, POP X.
Re-read: Lesson 1.1.2 — 3-, 2-, 1- and 0-address machines: register, accumulator and stack code
Q4 Answer: 143362 marks
2²⁴ − 200 × 2¹⁶ = 16,777,216 − 13,107,200 = 3,670,016; ÷ 2⁸ = 14,336.
Re-read: Lesson 1.1.4 — Instruction encoding: opcode space, register fields, expanding opcodes
Q5 Answer: (A)1 mark
R1 − R2 = 0 → Z = 1; BNE needs Z = 0.
- (B) is wrong: BNE branches on Z = 0.
- (C) is wrong: BNE does not test C.
- (D) is wrong: The result is 0, so N = 0.
Re-read: Lesson 1.1.3 — Instruction types: data movement, ALU, shifts, compare and flags, branches and jumps
Q6 Answer: 9001 mark
EA = M[500] = 600; M[600] = 900.
Re-read: Lesson 1.2.1 — Immediate, register, direct, indirect and register-indirect modes
Q7 Answer: 4001 mark
EA = 100 + 200 = 300; M[300] = 400.
Re-read: Lesson 1.2.2 — Displacement modes: indexed, base, PC-relative; auto-increment and auto-decrement
Q8 Answer: 10082 marks
1028 − 20 = 1008.
Re-read: Lesson 1.2.2 — Displacement modes: indexed, base, PC-relative; auto-increment and auto-decrement
Q9 Answer: (C)1 mark
R1 ← 300 first; R0 = M[300] = 400.
- (A) is wrong: Uses M[400], the old address.
- (B) is wrong: Neither value is right.
- (D) is wrong: R1 must change.
Re-read: Lesson 1.2.2 — Displacement modes: indexed, base, PC-relative; auto-increment and auto-decrement
Q10 Answer: (A) (B) (D)2 marks
Constants use immediate mode.
- (C) is wrong: Direct reads memory at an address.
Re-read: Lesson 1.2.3 — Choosing modes: arrays, pointers, constants, relocatable code; memory references per mode
Q11 Answer: 72 marks
Fetches 3; data 2 + 1 + 1 = 4.
Re-read: Lesson 1.2.3 — Choosing modes: arrays, pointers, constants, relocatable code; memory references per mode
Q12 Answer: 252 marks
Setup 2 + loop 7 × 3 = 21 + end 2 (STORE, HALT) = 25.
Re-read: Lesson 1.3.1 — Tracing programs: registers, memory and flags; counting memory references and cycles
Q13 Answer: 3021 mark
300 + 2.
Re-read: Lesson 1.3.2 — Stack, subroutine call and return; RISC vs CISC
Q14 Answer: 19842 marks
2000 − 4 × (7 − 3) = 1984.
Re-read: Lesson 1.3.2 — Stack, subroutine call and return; RISC vs CISC
Q15 Answer: (C)2 marks
Each iteration costs 3 + 1 + 1 + 2 = 7 cycles: 3 + 12 × 7 = 87.
- (A) is wrong: Counts BNZ as 1 cycle (3 + 12 × 6).
- (B) is wrong: Forgets the 3 setup cycles.
- (D) is wrong: Uses 8 cycles per iteration.
Re-read: Lesson 1.3.1 — Tracing programs: registers, memory and flags; counting memory references and cycles