Handling data hazards: stalling, operand forwarding, the load-use hazard

0 · Recall Warm-up

Answer from memory first. Answers are in the Answer Vault at the bottom.

• Which dependence causes hazards in the in-order 5-stage pipeline? from Lesson 5.2.2
• Total cycles with stalls? from Lesson 5.2.1
• What do the four pipeline registers sit between? from Lesson 5.1.3

1 · The Hook

🎣

ADD R1, R2, R3 computes its result at the end of EX in cycle 3, but writes it into R1 only in cycle 5. The next instruction wants R1 in cycle 4. Waiting costs 2 cycles. But the value already exists inside the pipeline, in a pipeline register. Route it straight to the ALU input, and the wait disappears: forwarding.

2 · Predict First

🤔

ADD R1, R2, R3 followed immediately by SUB R4, R1, R5. Without forwarding (registers written in WB, first half; read in ID, second half), how many stall cycles? With forwarding?

Make a guess in your head. The answer opens Section 3.

3 · Core Concept

💡

Predict First — the answer

Without forwarding: SUB's ID must line up with ADD's WB (cycle 5), but it would normally be in ID in cycle 3: 2 stalls. With forwarding from EX/MEM to the ALU input: 0 stalls.

Stalling (no forwarding)

The consumer reads registers in ID; the producer writes in WB. With the split-cycle register file, the consumer's ID may share the producer's WB cycle.

Stalls for a consumer d instructions after its producer (d = 1 means "next instruction"):

Operand forwarding (bypassing)

Extra paths carry a result from the EX/MEM or MEM/WB pipeline register back to the ALU inputs; MUXes choose the forwarded value over the stale register value.

• ALU → ALU: result at the end of EX, consumer's EX in the next cycle: 0 stalls.
• Load → use (load-use hazard): the loaded value exists only at the end of MEM; a consumer immediately after needs it at the start of its EX, one cycle too early: 1 stall even with forwarding. Two instructions later: 0 stalls.
• A store needs its data only in MEM, so it can receive a forwarded value later.

Worked example (5-stage, forwarding vs not)

I1: LOAD  R1, 0(R2)
I2: ADD   R3, R1, R4
I3: SUB   R5, R3, R6
I4: STORE R5, 8(R2)

With forwarding: one load-use stall before I2's EX; I3 and I4 get forwarded values: 9 cycles (8 ideal + 1).

Without forwarding: I2 waits for I1's WB (cycle 5), I3 for I2's WB, I4 for I3's WB: 14 cycles.

Compiler scheduling

Reorder independent instructions into the slot after a load: LOAD R1; LOAD R4; ADD R2, R1, R3; ADD R5, R4, R2 has no load-use stall that the original order LOAD R1; ADD R2, R1, R3; LOAD R4; ADD R5, R4, R2 had (two stalls, 10 cycles → 8 cycles).

4 · Visual

Forwarding paths (5-stage pipeline)

 IF | ID |  EX  | MEM | WB
          ^  |      |
          |  +--EX/MEM result---+     ALU result of the previous instruction
          +-----MEM/WB result---+     loaded value / result from two instructions back
          ALU input MUX picks the forwarded value

5 · Worked Examples

Example 1 Easy

With forwarding, how many stalls between ADD R1, R2, R3 and the very next ADD R5, R1, R1?

Solution

0 (ALU to ALU forwarding).

Example 2 Medium

With forwarding, how many stalls between LOAD R1, 0(R2) and the very next ADD R3, R1, R1?

Solution

1 (load-use hazard).

Example 3 GATE

Without forwarding, split-cycle register file, how many cycles does this take? ADD R1, R2, R3 · ADD R4, R5, R6 · ADD R7, R1, R4 · ADD R8, R7, R7

Solution

I3 needs R4 from I2 (distance 1): 2 stalls. I4 needs R7 from I3 (distance 1): 2 stalls. (R1 from I1 is distance 2, already covered by those stalls.) 8 + 4 = 12 cycles. With forwarding: 8.

6 · GATE Traps

⚠️

• Distance 1 without forwarding: 2 stalls (split register file), 3 without the split.
• Forwarding removes ALU→ALU stalls but not the load-use stall (1 cycle).
• Stalls already inserted for one dependence may cover another; trace the diagram.
• A store's data is needed in MEM, not EX.

7 · Memory Hook

🧠

"Forward what you've computed; a load is one step late."

8 · Connect the Dots

Data hazards are handled; the remaining hazard is about which instruction comes next. Next: branches, their penalty, and prediction and delayed branches.

9 · Self-Test

GATE format. Try every question before opening the vault.

Q1NAT2 marksWith forwarding

With forwarding (5-stage), how many cycles? LOAD R2, 0(R1) · ADD R3, R2, R2 · ADD R4, R3, R1 · ADD R5, R0, R0

Numerical answer: ________

Q2NAT2 marksWithout forwarding

Same code without forwarding (split-cycle register file). Cycles?

Numerical answer: ________

Q3NAT2 marksNo split

ADD R1, R2, R3 · ADD R4, R5, R6 · ADD R7, R1, R4 · ADD R8, R7, R7, without forwarding and without the split-cycle register file. Cycles?

Numerical answer: ________

Q4NAT2 marksLoad-use count

With forwarding: LOAD R1, 0(R0) · ADD R2, R1, R3 · LOAD R4, 4(R0) · ADD R5, R4, R2. Cycles?

Numerical answer: ________

Q5MCQ1 markScheduling

Reordering the previous code to LOAD R1 · LOAD R4 · ADD R2, R1, R3 · ADD R5, R4, R2 (with forwarding) gives how many cycles?

• (A) 9
• (B) 10
• (C) 8
• (D) 12

10 · Rule Card

• No forwarding, split RF: stalls 2/1/0 for distance 1/2/3 (no split: 3/2/1).
• Forwarding: ALU→ALU 0 stalls; load→next use 1 stall; distance 2 after a load: 0.
• Cycles = k + n − 1 + stalls; draw the diagram when dependences overlap.
• Scheduling independent instructions after loads hides the load-use stall.

11 · Concept Ledger

Unlocked in this lesson. From here on, these terms may be used.

stall-based interlockoperand forwarding (bypassing)forwarding paths EX/MEM and MEM/WBload-use hazardstall table by distanceinstruction scheduling

12 · Answer Vault