Phase 5 Checkpoint: 15 questions on pipelining. The 5-stage pipeline is IF ID EX MEM WB with a split-cycle register file unless stated.
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15 questions · 26 marks · 45 minutes. Negative marking on MCQ only: −1/3 mark for a wrong 1-mark MCQ, −2/3 for a wrong 2-mark MCQ. No negative marking for MSQ or NAT; MSQ has no partial credit.
Q1NAT1 markCycles
A 7-stage pipeline runs 64 instructions with no stalls. Cycles?
Numerical answer: ________
Q2NAT2 marksTime
Stages 30, 45, 40, 35 ns; latch 5 ns. Time for 200 instructions (μs)?
Numerical answer: ________
Q3NAT2 marksSpeedup
Same pipeline; large-n speedup over non-pipelined?
Numerical answer: ________
Q4NAT1 markEfficiency
Balanced 4-stage pipeline, 397 instructions. Efficiency?
Numerical answer: ________
Q5MCQ1 markStages
A load's memory read happens in:
- (A) EX
- (B) ID
- (C) MEM
- (D) WB
Q6NAT2 marksStall speedup
Balanced 10-stage pipeline; 30% of instructions incur 2 stalls. Speedup over non-pipelined?
Numerical answer: ________
Q7NAT2 marksDependences
How many RAW dependences: ADD R1, R2, R3 · ADD R2, R1, R1 · ADD R3, R2, R1 · ADD R1, R3, R2?
Numerical answer: ________
Q8NAT2 marksForwarding
With forwarding: LOAD R1, 0(R0) · ADD R2, R1, R1 · ADD R3, R2, R1 · LOAD R4, 0(R3) · ADD R5, R4, R4. Cycles?
Numerical answer: ________
Q9NAT2 marksNo forwarding
ADD R1, R2, R3 · SUB R4, R1, R5 · OR R6, R7, R8 · AND R9, R4, R6 without forwarding (split RF). Cycles?
Numerical answer: ________
Q10NAT1 markBranch penalty
Branches resolved at the end of stage 5 of an 8-stage pipeline, stall on branch. Penalty?
Numerical answer: ________
Q11NAT2 marksBranch CPI
22% branches, 50% taken, penalty 2, predict-not-taken. CPI?
Numerical answer: ________
Q12NAT2 marksTaken branch
5-stage pipeline (S1–S5), stage delays 10, 12, 9, 11, 8 ns, latch 1 ns. 10 instructions; I3 is a branch taken to I8, resolved at the end of S3; stall until resolved. Total time (ns)?
Numerical answer: ________
Q13NAT2 marksTable
| S1 | S2 | S3 | S4 | |
|---|---|---|---|---|
| I1 | 2 | 1 | 1 | 1 |
| I2 | 1 | 3 | 2 | 2 |
| I3 | 2 | 1 | 1 | 3 |
| I4 | 1 | 2 | 2 | 2 |
Cycles for I1–I4 once?
Numerical answer: ________
Q14NAT2 marksCompare
P: CPI 1.5 at 2 GHz; Q: CPI 1.2 at 1.5 GHz. Ratio of Q's time per instruction to P's?
Numerical answer: ________
Q15MSQ2 marksFacts
Which are true for the 5-stage pipeline with full forwarding?
- (A) An ALU result can be used by the next instruction without stalling.
- (B) WAR dependences cause stalls.
- (C) Forwarding also removes branch penalties.
- (D) A load followed by a dependent instruction needs 1 stall.
✓Answer Vault
Answer Vault
Try the questions first. Open when you are ready to check.
Q1 Answer: 701 mark
7 + 63.
Re-read: Lesson 5.1.1 — The pipeline idea: stages, latches, cycle time, k + n − 1 cycles
Q2 Answer: 10.152 marks
τ = 50 ns; (4 + 199) × 50 = 10,150 ns.
Re-read: Lesson 5.1.1 — The pipeline idea: stages, latches, cycle time, k + n − 1 cycles
Q3 Answer: 32 marks
150 / 50.
Re-read: Lesson 5.1.2 — Speedup, efficiency, throughput; unequal stages, latch delay, splitting stages
Q4 Answer: 0.99251 mark
397 / 400.
Re-read: Lesson 5.1.2 — Speedup, efficiency, throughput; unequal stages, latch delay, splitting stages
Q5 Answer: (C)1 mark
EX computes the address; MEM reads.
- (A) is wrong: Address only.
- (B) is wrong: Reads registers.
- (D) is wrong: Writes the register.
Re-read: Lesson 5.1.3 — The 5-stage RISC pipeline IF ID EX MEM WB; space–time diagrams
Q6 Answer: 6.252 marks
10 / 1.6.
Re-read: Lesson 5.2.1 — Structural hazards and stalls; CPI and speedup with stalls
Q7 Answer: 52 marks
I1→I2 (R1), I1→I3 (R1), I2→I3 (R2), I2→I4 (R2), I3→I4 (R3).
Re-read: Lesson 5.2.2 — Data dependences: RAW, WAR, WAW; finding them in code
Q8 Answer: 112 marks
Two load-use stalls: 5 + 4 + 2.
Re-read: Lesson 5.2.3 — Handling data hazards: stalling, operand forwarding, the load-use hazard
Q9 Answer: 122 marks
I2 needs R1 at distance 1: 2 stalls (I2's EX in cycle 6, WB 8). I3 follows (EX 7, WB 9). I4 needs R6 from I3 at distance 1: its ID must reach cycle 9, so EX 10, WB 12. 8 + 4 = 12.
Re-read: Lesson 5.2.3 — Handling data hazards: stalling, operand forwarding, the load-use hazard
Q10 Answer: 41 mark
5 − 1.
Re-read: Lesson 5.2.4 — Control hazards: branch penalty, flushing, prediction, delayed branch
Q11 Answer: 1.222 marks
1 + 0.22 × 0.5 × 2.
Re-read: Lesson 5.2.4 — Control hazards: branch penalty, flushing, prediction, delayed branch
Q12 Answer: 1562 marks
τ = 12 + 1 = 13 ns. Executed: I1, I2, I3, I8, I9, I10. I3 finishes S3 in cycle 5, so I8 is fetched in cycle 6 and I10 finishes S5 in cycle 12. 12 × 13 = 156 ns.
Re-read: Lesson 5.2.4 — Control hazards: branch penalty, flushing, prediction, delayed branch
Q13 Answer: 152 marks
I4 finishes S4 in cycle 15.
Re-read: Lesson 5.3.1 — Full cycle counting: mixed hazards and multi-cycle stages
Q14 Answer: 1.06 to 1.072 marks
Q: 1.2 / 1.5 GHz = 0.8 ns; P: 1.5 / 2 GHz = 0.75 ns; 0.8 / 0.75 ≈ 1.067.
Re-read: Lesson 5.3.2 — Pipeline performance from an instruction mix: effective CPI, comparing designs
Q15 Answer: (A) (D)2 marks
Forwarding handles data; WAR cannot occur in-order.
- (B) is wrong: In-order pipelines never see WAR hazards.
- (C) is wrong: Branches are control hazards.
Re-read: Lesson 5.2.3 — Handling data hazards: stalling, operand forwarding, the load-use hazard