Phase 3 Checkpoint: 15 questions on control units.
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15 questions · 22 marks · 40 minutes. Negative marking on MCQ only: −1/3 mark for a wrong 1-mark MCQ, −2/3 for a wrong 2-mark MCQ. No negative marking for MSQ or NAT; MSQ has no partial credit.
Q1NAT1 markStep counter
The longest instruction needs 33 steps. Step-counter bits?
Numerical answer: ________
Q2NAT2 marksInstruction time
At 2 GHz, an instruction takes 10 steps and waits 6 extra cycles for memory. Time in ns?
Numerical answer: ________
Q3MCQ1 markWMFC
While WMFC is active and MFC has not arrived:
- (A) the instruction is aborted
- (B) the step counter holds its value
- (C) End is asserted
- (D) the step counter advances anyway
Q4NAT2 marksSignal count
16 GPRs with Rin and Rout; 30 other signals. Total?
Numerical answer: ________
Q5MCQ1 markHardwired equation
In single-bus fetch step 3 (MDRout, IRin) the equation for MDRout must contain the term:
- (A) T1
- (B) T3·ADDreg
- (C) T3
- (D) T6·ADDmem
Q6NAT1 markDecoder
A 5-bit opcode fully decoded gives how many lines?
Numerical answer: ________
Q7MSQ2 marksHardwired
Which properties belong to hardwired control?
- (A) Built from logic gates and decoders
- (B) Fast
- (C) Common in RISC designs
- (D) Easy to change
Q8NAT2 marksCM size
Fetch: 4 microinstructions. 128 instructions × 6 execute microinstructions. Width 40 bits. CM bits?
Numerical answer: ________
Q9NAT1 markRuns
Fetch 3 microinstructions; an instruction's routine has 9. Microinstructions executed when it runs once?
Numerical answer: ________
Q10NAT2 marksVertical
Groups of mutually exclusive signals: 3, 3, 6, 10, 20 (idle allowed). Vertical width?
Numerical answer: ________
Q11MCQ1 markFormats
Horizontal microinstructions are preferred when:
- (A) the datapath has very few signals that are never active together
- (B) decoding hardware is free
- (C) control memory must be as small as possible
- (D) maximum parallelism and speed are needed
Q12NAT1 markAlways-active
A group of 32 mutually exclusive signals with exactly one always active. Bits?
Numerical answer: ________
Q13NAT2 marksNext-address width
Microinstruction width 40 bits; control field 26 bits; 8 conditions selectable. Maximum CM words?
Numerical answer: ________
Q14NAT2 marksMinimum width
Control field 20 bits (vertical); 5 conditions; CM of 1,500 words. Minimum width?
Numerical answer: ________
Q15MCQ1 markComparison
Which pairing is typical?
- (A) RISC – microprogrammed; CISC – hardwired
- (B) Both always hardwired
- (C) Both always microprogrammed
- (D) RISC – hardwired; CISC – microprogrammed
✓Answer Vault
Answer Vault
Try the questions first. Open when you are ready to check.
Q1 Answer: 61 mark
⌈log₂ 33⌉ = 6.
Re-read: Lesson 3.1.1 — Control signals, control steps and the step counter: what a control unit must produce
Q2 Answer: 82 marks
16 cycles × 0.5 ns.
Re-read: Lesson 3.1.1 — Control signals, control steps and the step counter: what a control unit must produce
Q3 Answer: (B)1 mark
The counter's enable is NOT(WMFC) + MFC.
- (A) is wrong: Nothing is aborted.
- (C) is wrong: The instruction continues after MFC.
- (D) is wrong: It must wait for memory.
Re-read: Lesson 3.1.1 — Control signals, control steps and the step counter: what a control unit must produce
Q4 Answer: 622 marks
32 + 30.
Re-read: Lesson 3.1.1 — Control signals, control steps and the step counter: what a control unit must produce
Q5 Answer: (C)1 mark
Fetch steps apply to every instruction. (MDRout also appears in later execute steps, e.g. T6·ADDmem.)
- (A) is wrong: MDRout is not active in T1.
- (B) is wrong: The fetch term has no instruction factor.
- (D) is wrong: That is an execute term, not the fetch term.
Re-read: Lesson 3.1.2 — Hardwired control: decoder, step counter and signal equations
Q6 Answer: 321 mark
2⁵.
Re-read: Lesson 3.1.2 — Hardwired control: decoder, step counter and signal equations
Q7 Answer: (A) (B) (C)2 marks
Hard to change.
- (D) is wrong: Changes need a redesign.
Re-read: Lesson 3.1.2 — Hardwired control: decoder, step counter and signal equations
Q8 Answer: 308802 marks
(4 + 768) × 40 = 30,880.
Re-read: Lesson 3.2.1 — Microprogrammed control: control memory, control words, microroutines, µPC
Q9 Answer: 121 mark
3 + 9.
Re-read: Lesson 3.2.1 — Microprogrammed control: control memory, control words, microroutines, µPC
Q10 Answer: 162 marks
⌈log₂ 4⌉ + ⌈log₂ 4⌉ + ⌈log₂ 7⌉ + ⌈log₂ 11⌉ + ⌈log₂ 21⌉ = 2 + 2 + 3 + 4 + 5 = 16.
Re-read: Lesson 3.2.2 — Microinstruction formats: horizontal vs vertical, field encoding, control-memory size
Q11 Answer: (D)1 mark
One bit per signal allows any combination at once, with no decode.
- (A) is wrong: Irrelevant to the choice.
- (B) is wrong: Free decoders would favour vertical encoding, not horizontal.
- (C) is wrong: Vertical is smaller.
Re-read: Lesson 3.2.2 — Microinstruction formats: horizontal vs vertical, field encoding, control-memory size
Q12 Answer: 51 mark
log₂ 32.
Re-read: Lesson 3.2.2 — Microinstruction formats: horizontal vs vertical, field encoding, control-memory size
Q13 Answer: 20482 marks
40 − 26 − 3 = 11 bits → 2,048.
Re-read: Lesson 3.2.3 — Microprogram sequencing: next-address field, conditional branches; hardwired vs microprogrammed
Q14 Answer: 342 marks
20 + 3 + 11 = 34.
Re-read: Lesson 3.2.3 — Microprogram sequencing: next-address field, conditional branches; hardwired vs microprogrammed
Q15 Answer: (D)1 mark
Simple ISAs suit fast hardwired logic; complex ISAs suit microcode.
- (A) is wrong: Reversed.
- (B) is wrong: Many CISC CPUs use microcode.
- (C) is wrong: RISC is usually hardwired.
Re-read: Lesson 3.2.3 — Microprogram sequencing: next-address field, conditional branches; hardwired vs microprogrammed