Instruction = opcode + operands; instruction formats; the instruction cycle

0 · Recall Warm-up

Answer from memory first. Answers are in the Answer Vault at the bottom.

• How many bits identify one of 50 things? from Lesson 0.2.1
• Little-endian: 0x11223344 at address 0. Byte at address 0? from Lesson 0.2.4
• What does the PC hold right after an instruction is fetched? from Lesson 0.1.1

1 · The Hook

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An instruction is just a number in memory, say 32 bits. Somewhere inside those bits the CPU must find what to do and what to do it to. Designing that layout is a budget problem: every bit given to one field is taken from another. GATE asks these budget questions almost every year.

2 · Predict First

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A processor has 50 different operations and 32 registers. Every instruction is 32 bits long and holds an operation code, two register numbers and a constant. How many bits are left for the constant?

Make a guess in your head. The answer opens Section 3.

3 · Core Concept

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Predict First — the answer

Operation code: ⌈log₂ 50⌉ = 6 bits. Each register number: log₂ 32 = 5 bits, so 10 bits for two. Constant: 32 − 6 − 10 = 16 bits.

Opcode and operands

A machine instruction is a bit pattern with fields:

• the opcode (operation code) says what to do: ADD, LOAD, JUMP …;
• operand fields say where the data is or where the result goes: a register number, a memory address, or a constant written into the instruction itself (an immediate value);
• sometimes mode bits say how to interpret an operand field (Chapter 1.2).

Field sizes come from counting (Lesson 0.2.1):

• opcode bits = ⌈log₂(number of distinct operations)⌉ (when every instruction uses the same opcode width);
• register field = ⌈log₂(number of registers)⌉;
• memory address field = number of address bits;
• whatever remains can hold an immediate; an n-bit immediate holds 0 … 2ⁿ − 1 unsigned, or −2ⁿ⁻¹ … 2ⁿ⁻¹ − 1 in two's complement.

Instruction formats

A format is one fixed arrangement of fields. A typical 32-bit machine has a few:

Fixed-length instructions (all 32 bits) are easy to fetch and decode. Variable-length instructions (1 to 15 bytes on x86) save memory but make fetching and decoding harder: the CPU must decode the first part to know how long the instruction is.

Notation used in these notes

• ADD R1, R2, R3 means R1 ← R2 + R3: destination first.
• LOAD R1, X means R1 ← M[X] (M[X] = contents of memory location X); STORE R1, X means M[X] ← R1.
• #5 is the constant 5 (immediate).

The instruction cycle in detail

Lesson 0.1.1's loop, with names GATE uses:

• IF, instruction fetch: read the instruction at PC; PC ← PC + instruction length.
• ID, instruction decode: find the opcode and fields.
• OA, operand address calculation: work out where each memory operand is (its effective address, Chapter 1.2).
• OF, operand fetch: read operands from registers or memory.
• EX, execute: the ALU does the operation.
• WB / SR, write back / store result: to a register or memory.

Then the CPU checks whether an I/O device is asking for attention (interrupts, Phase 6) and starts again. A memory reference happens in IF (always, once per instruction word), in OF (for memory operands) and in SR (for memory results).

4 · Visual

32-bit immediate format for "ADD R1, R2, #7"

 31      26 25    21 20    16 15                         0
+----------+--------+--------+----------------------------+
|  opcode  |   rd   |   rs   |        immediate           |
|  6 bits  | 5 bits | 5 bits |         16 bits            |
+----------+--------+--------+----------------------------+
   ADD        R1       R2              7

Instruction cycle:  IF -> ID -> OA -> OF -> EX -> WB/SR -> (check for interrupts) -> IF ...
memory used in:     IF always;   OF if an operand is in memory;   SR if the result goes to memory

5 · Worked Examples

Example 1 Easy

A machine has 64 registers and 32-bit instructions with a 7-bit opcode and three register fields. How many bits are unused?

Solution

Three register fields: 3 × 6 = 18 bits. Unused: 32 − 7 − 18 = 7 bits.

Example 2 Medium

A 24-bit instruction has an opcode, two register operands and an unsigned immediate. There are 45 instructions and 32 registers. What is the largest immediate value?

Solution

Opcode ⌈log₂ 45⌉ = 6; registers 2 × 5 = 10; immediate 24 − 16 = 8 bits → largest value 2⁸ − 1 = 255.

Example 3 GATE

A program of 200 fixed-length 4-byte instructions is loaded at byte address 0x1000. What is the address of its last instruction?

Solution

The last is instruction number 199 (counting from 0): 0x1000 + 199 × 4 = 4096 + 796 = 4892 = 0x131C.

6 · GATE Traps

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• Opcode bits use the ceiling: 45 operations need 6 bits, not 5.
• A signed n-bit immediate reaches only 2ⁿ⁻¹ − 1, half the unsigned maximum.
• "Instruction number k" from a start address: start + k × length when counting from 0; the last of N instructions is at start + (N − 1) × length.
• Every instruction makes at least one memory reference: its own fetch.

7 · Memory Hook

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"Opcode says what, operands say where, the rest is a constant." Subtract field widths from the instruction length.

8 · Connect the Dots

This lesson laid out the fields of one instruction. Next: how many operand fields an instruction should have, from three addresses down to zero, and how the same expression looks on each kind of machine.

9 · Self-Test

GATE format. Try every question before opening the vault.

Q1NAT1 markOpcode count

A 16-bit instruction has an opcode and three register fields; the machine has 8 registers. What is the maximum number of distinct opcodes?

Numerical answer: ________

Q2NAT2 marksSigned immediate

A 32-bit instruction has a 7-bit opcode, two register fields for 64 registers, and a two's-complement immediate in the remaining bits. What is the largest positive immediate?

Numerical answer: ________

Q3MCQ1 markCycle order

In the instruction cycle, which step must come before operand fetch for a memory operand?

• (A) Write back
• (B) Operand address calculation
• (C) Interrupt check
• (D) Execute

Q4NAT2 marksVariable length

A word-addressable machine has one-word and two-word instructions. A program has 20 one-word and 10 two-word instructions and starts at address 100. What is the first address after the program?

Numerical answer: ________

Q5MSQ2 marksFixed vs variable length

Which statements are true?

• (A) Fixed-length instructions simplify fetch and decode.
• (B) Variable-length instructions can make programs smaller.
• (C) With variable-length instructions, the CPU knows each instruction's length before reading any of it.
• (D) Every instruction is fetched from memory at least once per execution.

10 · Rule Card

• Instruction = opcode + operand fields (+ mode bits). Opcode bits = ⌈log₂ #ops⌉; register field = ⌈log₂ #regs⌉.
• Immediate = leftover bits: unsigned max 2ⁿ−1; signed −2ⁿ⁻¹ … 2ⁿ⁻¹−1.
• Instruction k (from 0) of fixed length L at start S: S + k·L.
• Cycle: IF → ID → OA → OF → EX → WB/SR → interrupt check. IF always references memory.
• Notation: destination first; M[X] = contents of location X; #c = constant.

11 · Concept Ledger

Unlocked in this lesson. From here on, these terms may be used.

machine instructionopcodeoperand fieldimmediate operandinstruction formatfixed vs variable lengthM[X] notationIF, ID, OA, OF, EX, WB/SRmemory reference

12 · Answer Vault