The last mixed set. After it, do the pattern drill (7.3.1) and then the final test.
⏱️
12 questions · 22 marks · 40 minutes. Negative marking on MCQ only: −1/3 mark for a wrong 1-mark MCQ, −2/3 for a wrong 2-mark MCQ. No negative marking for MSQ or NAT; MSQ has no partial credit.
Q1NAT2 marksPC-relative
A 4-byte branch instruction is at address 0x1F00 and must jump to 0x1E80. PC-relative byte offset (signed decimal)?
Numerical answer: ________
Q2NAT1 markOverflow
A 4-bit ALU adds 1100 and 1011 (two's complement). What is V (0 or 1)?
Numerical answer: ________
Q3NAT2 marksBlock CLA
A 16-bit adder of four 4-bit CLA blocks rippled together; g/p take 1 gate delay; each block's carry-out is ready 2 gate delays after its carry-in. When is c₁₆ ready (gate delays)?
Numerical answer: ________
Q4NAT2 marksSignal count
A single-bus CPU has 24 general-purpose registers with Rin and Rout each, plus 28 other control signals. Horizontal microinstruction control-field width?
Numerical answer: ________
Q5NAT2 marksRefresh
A DRAM has 4,096 rows, each refreshed every 8 ms; a row refresh takes 50 ns. Percentage of time spent refreshing?
Numerical answer: ________
Q6NAT2 marksSet-associative trace
A 4-line 2-way set-associative LRU cache receives blocks 0, 5, 8, 0, 13, 5, 8, 0. Number of misses?
Numerical answer: ________
Q7NAT2 marksTwo-level AMAT
L1 1 ns, 92% hits; L2 10 ns, local hit ratio 75%; memory 120 ns. Hierarchical AMAT (ns)?
Numerical answer: ________
Q8NAT2 marksArray misses
double A[64][64] at address 0, a 4 KB direct-mapped cache with 64-byte blocks, column-wise traversal. Number of misses?
Numerical answer: ________
Q9NAT2 marksStall speedup
A balanced 7-stage pipeline without overhead; 10% of instructions incur 4 stall cycles. Speedup over non-pipelined?
Numerical answer: ________
Q10NAT2 marksInterrupt gain
A device sends one byte every 60 µs; interrupt overhead is 4 µs per byte. Gain of interrupt mode over program-controlled mode?
Numerical answer: ________
Q11MCQ1 markMemory-mapped I/O
Which is a disadvantage of memory-mapped I/O?
- (A) It uses up part of the memory address space
- (B) It needs special IN/OUT instructions
- (C) It requires DMA
- (D) It cannot use addressing modes
Q12NAT2 marksProgram cycles
MOV R1, #0 (1) · MOV R2, #25 (1) · LOOP: ADD R1, R1, R2 (1) · SUB R2, R2, #1 (1) · BNZ R2, LOOP (2) · STORE R1, X (3) · HALT (1). Cycle costs in brackets. Total cycles?
Numerical answer: ________
✓Answer Vault
Answer Vault
Try the questions first. Open when you are ready to check.
Q1 Answer: -1322 marks
PC = 0x1F04 = 7,940; target 7,808; offset −132.
Re-read: Lesson 1.2.2 — Displacement modes: indexed, base, PC-relative; auto-increment and auto-decrement
Q2 Answer: 11 mark
−4 + −5 = −9 does not fit; result 0111; c₃ = 0, c₄ = 1 → V = 1.
Re-read: Lesson 2.1.1 — Building an ALU: 1-bit slice, n-bit ALU, subtraction, flags Z N C V
Q3 Answer: 92 marks
1 + 4 × 2.
Re-read: Lesson 2.1.2 — Adder speed: ripple-carry delay, carry-lookahead (generate, propagate), gate-delay counting
Q4 Answer: 762 marks
48 + 28.
Re-read: Lesson 3.1.1 — Control signals, control steps and the step counter: what a control unit must produce
Q5 Answer: 2.562 marks
4096 × 50 ns = 204.8 µs; / 8 ms.
Re-read: Lesson 4.1.3 — Memory chips: SRAM vs DRAM, ROM types, DRAM refresh; chip organisation 2ᵏ × n
Q6 Answer: 42 marks
Set 0 (even): 0 M, 8 M, 0 H, 8 H, 0 H. Set 1 (odd): 5 M, 13 M, 5 H.
Re-read: Lesson 4.2.5 — Replacement policies: LRU, FIFO, random, optimal; tracing sets
Q7 Answer: 4.22 marks
1 + 0.08 × (10 + 0.25 × 120) = 1 + 0.08 × 40.
Re-read: Lesson 4.3.3 — Multilevel caches: L1 and L2, local vs global miss rate, inclusion
Q8 Answer: 40962 marks
Rows are 512 B = 8 blocks apart; 64 lines → only 8 lines used by a column; nothing survives to the next column.
Re-read: Lesson 4.3.4 — Programs and caches: array layout, loop order, counting misses
Q9 Answer: 52 marks
7 / 1.4.
Re-read: Lesson 5.2.1 — Structural hazards and stalls; CPI and speedup with stalls
Q10 Answer: 152 marks
60 / 4.
Re-read: Lesson 6.2.2 — Interrupt-driven I/O: overhead per transfer; interrupts vs polling
Q11 Answer: (A)1 mark
Device ports take memory addresses.
- (B) is wrong: That is isolated I/O.
- (C) is wrong: Unrelated.
- (D) is wrong: All load/store modes work.
Re-read: Lesson 6.1.1 — I/O devices, interfaces and ports; memory-mapped vs I/O-mapped I/O; buses
Q12 Answer: 1062 marks
2 + 25 × 4 + 3 + 1.
Re-read: Lesson 1.3.1 — Tracing programs: registers, memory and flags; counting memory references and cycles