Phase 6 Checkpoint: 15 questions on I/O, interrupts and DMA.
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15 questions · 23 marks · 40 minutes. Negative marking on MCQ only: −1/3 mark for a wrong 1-mark MCQ, −2/3 for a wrong 2-mark MCQ. No negative marking for MSQ or NAT; MSQ has no partial credit.
Q1MCQ1 markMapping
Which statement holds for memory-mapped I/O?
- (A) Devices are accessed with IN/OUT only
- (B) It needs a separate I/O address bus
- (C) It enlarges memory
- (D) Device registers occupy part of the memory address space
Q2NAT1 markSpace
A 32-bit address space reserves 256 MB for memory-mapped I/O. How many MB remain?
Numerical answer: ________
Q3NAT2 marksPolling
A 2 GHz CPU polls a device 1,000,000 times per second at 300 cycles per poll. Percentage of CPU time?
Numerical answer: ________
Q4NAT2 marksMinimum polling
A device produces 400 KB/s (decimal) in 4-byte units. A 1 GHz CPU must poll once per unit at 200 cycles per poll. Percentage of CPU time?
Numerical answer: ________
Q5NAT1 markBusy-wait
A device sends a byte every 20 µs; the CPU busy-waits. CPU time (ms) for 10,000 bytes?
Numerical answer: ________
Q6NAT1 markReturn address
Byte-addressable; instructions from 400 with sizes 2, 4, 4, 6, 2 bytes. An interrupt arrives during the 3rd instruction. Return address?
Numerical answer: ________
Q7NAT1 markVector
Vector table base 0x100 (256), 4-byte entries, vector 20. Entry address (decimal)?
Numerical answer: ________
Q8MCQ1 markDaisy chain
Devices A, B, C, D are daisy-chained in that order from the CPU. C and D request together. Who is served first?
- (A) C
- (B) Whichever requested earlier by a few nanoseconds
- (C) D
- (D) Both
Q9MSQ2 marksInterrupt sequence
Which are part of servicing an enabled interrupt?
- (A) Saving the PC
- (B) Completing the current instruction
- (C) Restarting the current instruction from scratch afterwards
- (D) Running the ISR
Q10NAT2 marksGain
A device transfers 25 KB/s (decimal) byte-wise; interrupt overhead 8 µs. Gain over program-controlled mode?
Numerical answer: ________
Q11NAT2 marksInterrupt load
A 1 GHz CPU; 4 MB/s (decimal) device in 8-byte units; 400 cycles per interrupt; the device is active 25% of the time. Overall percentage of CPU time?
Numerical answer: ________
Q12NAT2 marksDMA overhead
DMA: 50 MB/s (decimal) device, 100,000-byte blocks, 1 GHz CPU spends 4,000 cycles per block. Percentage of CPU time?
Numerical answer: ________
Q13NAT2 marksCycle stealing
A 5 MB/s (decimal) device uses cycle stealing with 4-byte words, one stolen cycle per word, 200 MHz bus. Percentage of bus cycles stolen?
Numerical answer: ________
Q14NAT2 marksCount
An 8-bit count register counts 16-bit words. Minimum DMA operations to move 64 KB (65,536 bytes)?
Numerical answer: ________
Q15MCQ1 markModes
Which mode gives the fastest transfer of a block but blocks the CPU from memory meanwhile?
- (A) Burst
- (B) Cycle stealing
- (C) Transparent
- (D) Polling
✓Answer Vault
Answer Vault
Try the questions first. Open when you are ready to check.
Q1 Answer: (D)1 mark
Ports are memory addresses.
- (A) is wrong: Isolated I/O.
- (B) is wrong: No separate bus needed.
- (C) is wrong: It reduces available memory addresses.
Re-read: Lesson 6.1.1 — I/O devices, interfaces and ports; memory-mapped vs I/O-mapped I/O; buses
Q2 Answer: 38401 mark
4096 − 256.
Re-read: Lesson 6.1.1 — I/O devices, interfaces and ports; memory-mapped vs I/O-mapped I/O; buses
Q3 Answer: 152 marks
3×10⁸ / 2×10⁹.
Re-read: Lesson 6.1.2 — Programmed I/O: polling, busy-waiting and its CPU cost
Q4 Answer: 22 marks
100,000 polls × 200 = 2×10⁷.
Re-read: Lesson 6.1.2 — Programmed I/O: polling, busy-waiting and its CPU cost
Q5 Answer: 2001 mark
10,000 × 20 µs.
Re-read: Lesson 6.1.2 — Programmed I/O: polling, busy-waiting and its CPU cost
Q6 Answer: 4101 mark
Starts 400, 402, 406, 410.
Re-read: Lesson 6.2.1 — Interrupts: the interrupt cycle, ISR, context saving, vectored interrupts, priority and daisy chain
Q7 Answer: 3361 mark
256 + 80.
Re-read: Lesson 6.2.1 — Interrupts: the interrupt cycle, ISR, context saving, vectored interrupts, priority and daisy chain
Q8 Answer: (A)1 mark
Position decides.
- (B) is wrong: Timing within a cycle is not the rule.
- (C) is wrong: Farther from the CPU.
- (D) is wrong: Only one acknowledge.
Re-read: Lesson 6.2.1 — Interrupts: the interrupt cycle, ISR, context saving, vectored interrupts, priority and daisy chain
Q9 Answer: (A) (B) (D)2 marks
The current instruction already completed.
- (C) is wrong: Execution resumes at the next instruction.
Re-read: Lesson 6.2.1 — Interrupts: the interrupt cycle, ISR, context saving, vectored interrupts, priority and daisy chain
Q10 Answer: 52 marks
T_unit = 40 µs; 40 / 8.
Re-read: Lesson 6.2.2 — Interrupt-driven I/O: overhead per transfer; interrupts vs polling
Q11 Answer: 52 marks
500,000 × 400 = 2×10⁸ → 20% while active; × 0.25 = 5%.
Re-read: Lesson 6.2.2 — Interrupt-driven I/O: overhead per transfer; interrupts vs polling
Q12 Answer: 0.22 marks
Block time 2 ms; CPU 4 µs.
Re-read: Lesson 6.2.3 — DMA: the controller, burst mode, cycle stealing, transparent mode; CPU time lost
Q13 Answer: 0.6252 marks
1.25×10⁶ / 2×10⁸.
Re-read: Lesson 6.2.3 — DMA: the controller, burst mode, cycle stealing, transparent mode; CPU time lost
Q14 Answer: 1282 marks
32,768 words / 256.
Re-read: Lesson 6.2.3 — DMA: the controller, burst mode, cycle stealing, transparent mode; CPU time lost
Q15 Answer: (A)1 mark
The controller holds the bus for the whole block.
- (B) is wrong: Interleaves with the CPU.
- (C) is wrong: Uses idle cycles only.
- (D) is wrong: Not a DMA mode.
Re-read: Lesson 6.2.3 — DMA: the controller, burst mode, cycle stealing, transparent mode; CPU time lost