Phase 0 Checkpoint: 15 questions on everything in Phase 0. Work without the notes, then open the vault.
⏱️
15 questions · 22 marks · 40 minutes. Negative marking on MCQ only: −1/3 mark for a wrong 1-mark MCQ, −2/3 for a wrong 2-mark MCQ. No negative marking for MSQ or NAT; MSQ has no partial credit.
Q1MCQ1 markStored program
In a von Neumann machine, instructions and data:
- (A) are stored in separate memories
- (B) are distinguished by a tag bit in every word
- (C) are both kept in registers
- (D) share one memory and one path to it
Q2MCQ1 markAddress bus
The width of the address bus decides:
- (A) how many bits move per transfer
- (B) the number of registers
- (C) how many locations can be addressed
- (D) the clock rate
Q3NAT1 markCycle time
Cycle time in ns of a 800 MHz clock?
Numerical answer: ________
Q4NAT2 marksCPI
A program has 30% loads (4 cycles), 10% stores (3 cycles), 40% ALU (1 cycle) and 20% branches (2 cycles). CPI?
Numerical answer: ________
Q5NAT2 marksExecution time
With the CPI from the previous question, a 2.3 GHz processor runs 4.6 × 10⁹ instructions. Time in seconds?
Numerical answer: ________
Q6NAT2 marksAmdahl
Half of a program's time is spent in code that a new compiler makes 5 times faster. Overall speedup (2 decimals)?
Numerical answer: ________
Q7NAT1 markAddress bits
Byte-addressable 8 GB memory: address bits?
Numerical answer: ________
Q8NAT1 markHex
0x1F4 in decimal?
Numerical answer: ________
Q9MCQ1 markNegation
The 8-bit two's complement of 0101 1000 (88) is:
- (A) 1010 0111
- (B) 1010 1000
- (C) 1101 1000
- (D) 0101 1001
Q10MSQ2 marksOverflow
In 8-bit two's complement, which additions overflow?
- (A) 0100 0000 + 1100 0000
- (B) 1000 0001 + 1111 1111
- (C) 1001 0000 + 1010 0000
- (D) 0111 0000 + 0001 0000
Q11NAT2 marksBit field
A 32-bit instruction word is 0x8C4A0010. What unsigned value is in bits 25 to 21?
Numerical answer: ________
Q12NAT1 markDecoder
A memory is built from 16 chips; one decoder picks the chip. How many input lines does that decoder need?
Numerical answer: ________
Q13MCQ1 markTri-state
The purpose of tri-state buffers on a shared bus is to:
- (A) store the bus value between cycles
- (B) amplify the signal for long wires
- (C) let only one source drive the bus while others are disconnected
- (D) convert serial data to parallel
Q14NAT2 marksLittle-endian
The 32-bit value 0x00000102 is stored little-endian at address 40. What unsigned value is the byte at address 40?
Numerical answer: ________
Q15NAT2 marksWord-addressable capacity
A word-addressable memory with 32-bit words has capacity 4 MB. How many address bits does it need?
Numerical answer: ________
✓Answer Vault
Answer Vault
Try the questions first. Open when you are ready to check.
Q1 Answer: (D)1 mark
One memory, one path; the use decides whether a word is an instruction or data.
- (A) is wrong: That is Harvard.
- (B) is wrong: No tag bit exists; the PC decides what is fetched as an instruction.
- (C) is wrong: Registers hold only a few values.
Re-read: Lesson 0.1.1 — What a computer is: CPU, memory, I/O, buses; the stored-program idea; fetch–decode–execute
Q2 Answer: (C)1 mark
n address lines name 2ⁿ locations.
- (A) is wrong: That is the data bus width.
- (B) is wrong: Unrelated.
- (D) is wrong: Unrelated.
Re-read: Lesson 0.1.1 — What a computer is: CPU, memory, I/O, buses; the stored-program idea; fetch–decode–execute
Q3 Answer: 1.251 mark
1 / (8×10⁸) s = 1.25 ns.
Re-read: Lesson 0.1.2 — Performance: clock, cycle time, CPI, execution time, MIPS, speedup, Amdahl's law
Q4 Answer: 2.32 marks
0.3×4 + 0.1×3 + 0.4×1 + 0.2×2 = 1.2 + 0.3 + 0.4 + 0.4 = 2.3.
Re-read: Lesson 0.1.2 — Performance: clock, cycle time, CPI, execution time, MIPS, speedup, Amdahl's law
Q5 Answer: 4.62 marks
4.6×10⁹ × 2.3 / 2.3×10⁹ = 4.6 s.
Re-read: Lesson 0.1.2 — Performance: clock, cycle time, CPI, execution time, MIPS, speedup, Amdahl's law
Q6 Answer: 1.66 to 1.672 marks
1 / (0.5 + 0.1) = 1.6667.
Re-read: Lesson 0.1.2 — Performance: clock, cycle time, CPI, execution time, MIPS, speedup, Amdahl's law
Q7 Answer: 331 mark
2³ × 2³⁰ = 2³³.
Re-read: Lesson 0.2.1 — Binary and hex, powers of two, size units, log₂: n bits name 2ⁿ things
Q8 Answer: 5001 mark
1×256 + 15×16 + 4 = 500.
Re-read: Lesson 0.2.1 — Binary and hex, powers of two, size units, log₂: n bits name 2ⁿ things
Q9 Answer: (B)1 mark
Invert: 1010 0111; add 1: 1010 1000 (−88).
- (A) is wrong: Forgot to add 1 (that is the ones' complement).
- (C) is wrong: Only flips the sign bit.
- (D) is wrong: Adds 1 without inverting.
Re-read: Lesson 0.2.2 — Signed integers: 2's complement, ranges, sign extension, overflow; bit fields and shifts
Q10 Answer: (C) (D)2 marks
A: 112 + 16 = 128 > 127, overflow. D: −112 + (−96) = −208 < −128, overflow.
- (A) is wrong: Opposite signs never overflow.
- (B) is wrong: −127 + (−1) = −128, which is still in range.
Re-read: Lesson 0.2.2 — Signed integers: 2's complement, ranges, sign extension, overflow; bit fields and shifts
Q11 Answer: 22 marks
0x8C4A0010 >> 21 = 0x462; low 5 bits of 0x462 (100 0110 0010) = 00010 = 2.
Re-read: Lesson 0.2.2 — Signed integers: 2's complement, ranges, sign extension, overflow; bit fields and shifts
Q12 Answer: 41 mark
2⁴ = 16.
Re-read: Lesson 0.2.3 — Digital building blocks: gates, MUX, decoder, adder, flip-flops, registers, clock, tri-state bus
Q13 Answer: (C)1 mark
High impedance disconnects the idle sources.
- (A) is wrong: Registers store values.
- (B) is wrong: Not their role here.
- (D) is wrong: Unrelated.
Re-read: Lesson 0.2.3 — Digital building blocks: gates, MUX, decoder, adder, flip-flops, registers, clock, tri-state bus
Q14 Answer: 22 marks
Least significant byte 0x02 is at the lowest address.
Re-read: Lesson 0.2.4 — Memory as an array: address, word, byte vs word addressing, endianness, alignment
Q15 Answer: 202 marks
4 MB / 4 B = 2²² / 2² = 2²⁰ words → 20 bits.
Re-read: Lesson 0.2.4 — Memory as an array: address, word, byte vs word addressing, endianness, alignment