Twelve questions from all phases, mixed on purpose so you must first recognise which idea each needs. Conventions as in the front matter: byte-addressable memory, K = 2¹⁰ for sizes, decimal rates, 5-stage pipeline with a split-cycle register file.
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12 questions · 21 marks · 40 minutes. Negative marking on MCQ only: −1/3 mark for a wrong 1-mark MCQ, −2/3 for a wrong 2-mark MCQ. No negative marking for MSQ or NAT; MSQ has no partial credit.
Q1NAT2 marksExpanding opcode
16-bit instructions with 5-bit register fields. Type A: 1 instruction with three register fields. Type B: 20 instructions with two register fields. Type C has one register field. Maximum number of type-C instructions?
Numerical answer: ________
Q2NAT1 markIndirect addressing
Memory: M[100] = 300, M[300] = 500, M[500] = 100. What does LOAD R0, @100 load?
Numerical answer: ________
Q3NAT2 marksAMAT
Hierarchical access: t_c = 2 ns, t_m = 120 ns, h = 0.95. Average access time (ns)?
Numerical answer: ________
Q4NAT2 marksTag bits
32-bit addresses, a 128 KB 8-way set-associative cache with 32-byte blocks. Tag bits?
Numerical answer: ________
Q5NAT2 marksPipeline time
Stage delays 5, 7, 6, 8 ns; latch 1 ns. Time for 200 instructions (ns)?
Numerical answer: ________
Q6MCQ1 markMicroinstruction format
Which statement about vertical microinstructions is correct?
- (A) They use one bit per control signal.
- (B) They need no control memory.
- (C) They encode mutually exclusive signals into fields that must be decoded.
- (D) They allow more signals active at once than horizontal ones.
Q7NAT2 marksMicroinstruction width
Horizontal control field of 24 signals; a MUX selects one of 10 conditions; the control memory has 700 words. Minimum microinstruction width?
Numerical answer: ________
Q8NAT1 markBooth
Booth's algorithm with the 8-bit multiplier 0011 0110: total additions plus subtractions?
Numerical answer: ________
Q9NAT2 marksDirect-mapped trace
A 4-line direct-mapped cache receives blocks 3, 7, 3, 11, 7, 3. Number of misses?
Numerical answer: ________
Q10NAT2 marksDMA
DMA from a 4 MB/s (decimal) device in 8,000-byte blocks. The 500 MHz CPU spends 2,000 cycles per block. Percentage of CPU time?
Numerical answer: ________
Q11NAT2 marksForwarding
With full forwarding: LOAD R1, 0(R2) · ADD R3, R1, R1 · ADD R4, R3, R2 · LOAD R5, 0(R4) · ADD R6, R5, R3. Cycles?
Numerical answer: ________
Q12MSQ2 marksInterrupts
Which are true?
- (A) A vectored interrupt lets the CPU find the ISR without polling devices.
- (B) In a daisy chain the device farthest from the CPU has the highest priority.
- (C) An ISR must restore any registers it changed before returning.
- (D) The PC saved on an interrupt points to the instruction after the one that was executing.
✓Answer Vault
Answer Vault
Try the questions first. Open when you are ready to check.
Q1 Answer: 3842 marks
2¹⁶ − 1 × 2¹⁵ − 20 × 2¹⁰ = 65,536 − 32,768 − 20,480 = 12,288; ÷ 2⁵ = 384.
Re-read: Lesson 1.1.4 — Instruction encoding: opcode space, register fields, expanding opcodes
Q2 Answer: 5001 mark
EA = M[100] = 300; operand M[300] = 500.
Re-read: Lesson 1.2.1 — Immediate, register, direct, indirect and register-indirect modes
Q3 Answer: 82 marks
2 + 0.05 × 120.
Re-read: Lesson 4.1.2 — Average memory access time: hierarchical vs simultaneous access; multi-level formulas
Q4 Answer: 182 marks
Lines 4,096; sets 512 → 9 bits; offset 5; tag 32 − 14 = 18.
Re-read: Lesson 4.2.2 — Fully associative and set-associative mapping; comparators and multiplexers
Q5 Answer: 18272 marks
τ = 9; (4 + 199) × 9 = 1,827.
Re-read: Lesson 5.1.2 — Speedup, efficiency, throughput; unequal stages, latch delay, splitting stages
Q6 Answer: (C)1 mark
Encoding saves width at the cost of decoding.
- (A) is wrong: That is horizontal.
- (B) is wrong: Both formats live in control memory.
- (D) is wrong: Fewer signals can be active together.
Re-read: Lesson 3.2.2 — Microinstruction formats: horizontal vs vertical, field encoding, control-memory size
Q7 Answer: 382 marks
24 + ⌈log₂ 10⌉ + ⌈log₂ 700⌉ = 24 + 4 + 10.
Re-read: Lesson 3.2.3 — Microprogram sequencing: next-address field, conditional branches; hardwired vs microprogrammed
Q8 Answer: 41 mark
Recoded 0 +1 0 −1 +1 0 −1 0: 2 additions, 2 subtractions.
Re-read: Lesson 2.1.3 — Multiplication: shift-and-add, Booth's algorithm; restoring division
Q9 Answer: 62 marks
All map to line 3 and keep evicting each other.
Re-read: Lesson 4.2.4 — Tracing references: hits and misses; compulsory, capacity and conflict misses
Q10 Answer: 0.22 marks
Block time 2 ms; CPU time 4 µs; 0.2%.
Re-read: Lesson 6.2.3 — DMA: the controller, burst mode, cycle stealing, transparent mode; CPU time lost
Q11 Answer: 112 marks
Two load-use stalls: 5 + 4 + 2.
Re-read: Lesson 5.2.3 — Handling data hazards: stalling, operand forwarding, the load-use hazard
Q12 Answer: (A) (C) (D)2 marks
Nearest the CPU wins in a daisy chain.
- (B) is wrong: Reversed.
Re-read: Lesson 6.2.1 — Interrupts: the interrupt cycle, ISR, context saving, vectored interrupts, priority and daisy chain