GATE COA questions come back in a small number of shapes. For each shape: the cue in the question, the fastest method, and the lesson that teaches it.
| # | Pattern (cue) | Fastest method | Lesson |
|---|---|---|---|
| 1 | "bits for the immediate / opcode" | subtract ⌈log₂⌉ field widths from the instruction length | Lesson 1.1.1 |
| 2 | "maximum number of one-address instructions" | encodings: 2ʷ − Σ count·2^(operand bits), ÷ 2^(next operand bits) | Lesson 1.1.4 |
| 3 | memory table + mode → value loaded | count hops: # 0, direct 1, @ 2, (R) 1, d(R) 1 | Lesson 1.2.1 |
| 4 | "relative address field" | T − (X + L); word vs byte units | Lesson 1.2.2 |
| 5 | "memory references / cycles" for a program | setup + iterations × body + end; fetches + data | Lesson 1.3.1 |
| 6 | "return address pushed" | address of the instruction after the one in progress | Lesson 6.2.1 |
| 7 | "additions/subtractions in Booth" | append 0; count 10 (sub) and 01 (add) pairs | Lesson 2.1.3 |
| 8 | adder delay | ripple n·t_c; CLA 4 gate delays (unlimited fan-in), Θ(log n) bounded | Lesson 2.1.2 |
| 9 | single-bus control steps | one out per step; Y before, Z after; fetch 3 | Lesson 2.2.2 |
| 10 | microinstruction width / CM size | control + ⌈log₂ conditions⌉ + ⌈log₂ words⌉; vertical ⌈log₂(k+1)⌉ | Lesson 3.2.3 |
| 11 | average access time | hit/miss totals given → h·t_hit + (1−h)·t_miss; else hierarchical t_c + (1−h)t_m unless "simultaneous" | Lesson 4.1.2 |
| 12 | chips and decoder | (W/w)(B/b); decoder log₂(W/w) inputs | Lesson 4.1.4 |
| 13 | tag / index / offset | offset log₂ B; index log₂(lines ÷ ways); tag = rest | Lesson 4.2.2 |
| 14 | tag directory size | lines × (tag + V + D + replacement bits) | Lesson 4.2.3 |
| 15 | hits/misses for a sequence | block numbers; set = j mod S; LRU table | Lesson 4.2.4 |
| 16 | loop over a 2-D array | row-wise misses = bytes ÷ B; column-wise: check which lines a column uses | Lesson 4.3.4 |
| 17 | CPI with cache misses | base + accesses × miss rate × penalty (cycles) | Lesson 4.3.2 |
| 18 | pipeline time / speedup | (k + n − 1)τ; τ = max + latch; speedup → Σtᵢ ÷ τ | Lesson 5.1.2 |
| 19 | stalls with/without forwarding | no fwd 2/1/0 by distance; fwd 0, load-use 1 | Lesson 5.2.3 |
| 20 | branch penalty / CPI | r − 1; CPI = 1 + f·(p_taken)·penalty | Lesson 5.2.4 |
| 21 | per-instruction stage table | cell rule: max(own previous stage, previous instruction's same stage) | Lesson 5.3.1 |
| 22 | interrupt vs program-controlled | gain = time between units ÷ overhead | Lesson 6.2.2 |
| 23 | DMA CPU time / count register | CPU time per block ÷ block time; ⌈S ÷ 2ᵏ⌉ operations | Lesson 6.2.3 |
⏱️
Time budget in the exam
1-mark questions: under 90 seconds. 2-mark questions: under 3 minutes. If a cache question is taking longer, you have not yet written the address split; if a pipeline question is, draw the space–time table.
⏱️
8 questions · 14 marks · 45 minutes. Negative marking on MCQ only: −1/3 mark for a wrong 1-mark MCQ, −2/3 for a wrong 2-mark MCQ. No negative marking for MSQ or NAT; MSQ has no partial credit.
Q1NAT2 marksPattern 2
16-bit instructions, 4-bit register fields. 14 three-register and 30 two-register instructions exist. Maximum one-register instructions?
Numerical answer: ________
Q2NAT2 marksPattern 13
32-bit addresses, 64 KB 2-way set-associative cache, 32-byte blocks. Index bits?
Numerical answer: ________
Q3NAT1 markPattern 7
Booth's algorithm, 8-bit multiplier 0111 0110: number of subtractions?
Numerical answer: ________
Q4NAT2 marksPattern 18
Stages 10, 14, 12, 9 ns; latch 1 ns. Large-n speedup over non-pipelined (2 decimals)?
Numerical answer: ________
Q5NAT2 marksPattern 20
A 7-stage pipeline resolves branches at the end of stage 5 and stalls on every branch; 18% of instructions are branches. CPI?
Numerical answer: ________
Q6NAT2 marksPattern 23
A 16-bit byte count register; a file of 4,000 KB (4,096,000 bytes). Minimum DMA operations?
Numerical answer: ________
Q7NAT2 marksPattern 17
Base CPI 1.2; 1.25 memory accesses per instruction; miss rate 4%; penalty 100 cycles. Effective CPI?
Numerical answer: ________
Q8NAT1 markPattern 4
Word-addressable machine: a 2-word branch at address 400 must reach 350. Relative field value?
Numerical answer: ________
✓Answer Vault
Answer Vault
Try the questions first. Open when you are ready to check.
Q1 Answer: 322 marks
65,536 − 14 × 4,096 − 30 × 256 = 512; ÷ 16 = 32.
Re-read: Lesson 1.1.4 — Instruction encoding: opcode space, register fields, expanding opcodes
Q2 Answer: 102 marks
Lines 2,048; sets 1,024 → 10.
Re-read: Lesson 4.2.2 — Fully associative and set-associative mapping; comparators and multiplexers
Q3 Answer: 21 mark
Recoded +1 0 0 −1 +1 0 −1 0.
Re-read: Lesson 2.1.3 — Multiplication: shift-and-add, Booth's algorithm; restoring division
Q4 Answer: 3.02 marks
Σ = 45; τ = 15; 45 / 15 = 3.
Re-read: Lesson 5.1.2 — Speedup, efficiency, throughput; unequal stages, latch delay, splitting stages
Q5 Answer: 1.722 marks
Penalty 4; 1 + 0.18 × 4.
Re-read: Lesson 5.2.4 — Control hazards: branch penalty, flushing, prediction, delayed branch
Q6 Answer: 632 marks
4,096,000 / 65,536 = 62.5 → 63.
Re-read: Lesson 6.2.3 — DMA: the controller, burst mode, cycle stealing, transparent mode; CPU time lost
Q7 Answer: 6.22 marks
1.2 + 1.25 × 0.04 × 100.
Re-read: Lesson 4.3.2 — Miss penalty and block transfer; memory-stall cycles; CPI with cache misses
Q8 Answer: -521 mark
PC = 402; 350 − 402.
Re-read: Lesson 1.2.2 — Displacement modes: indexed, base, PC-relative; auto-increment and auto-decrement