Memory chips: SRAM vs DRAM, ROM types, DRAM refresh; chip organisation 2ᵏ × n

0 · Recall Warm-up

Answer from memory first. Answers are in the Answer Vault at the bottom.

• t_c = 10, t_m = 100, h = 0.9: hierarchical and simultaneous averages? from Lesson 4.1.2
• Temporal vs spatial locality? from Lesson 4.1.1
• What is a flip-flop? from Lesson 0.2.3

1 · The Hook

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Caches are built from SRAM, main memory from DRAM, and the boot code sits in flash. Why the split? One cell type is fast but big; the other is tiny but leaks its charge and must be refreshed thousands of times a second. GATE asks for refresh overheads and for the address and data lines of a chip.

2 · Predict First

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A DRAM cell stores a bit as charge on a tiny capacitor, which leaks away within milliseconds. What must the memory do to keep data, and what does that cost?

Make a guess in your head. The answer opens Section 3.

3 · Core Concept

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Predict First — the answer

It must refresh every row periodically (read it and write it back) before the charge fades. During a refresh, that part of the memory cannot serve the CPU, so a small fraction of time is lost.

RAM: SRAM vs DRAM

Both are volatile: data is lost without power.

ROM family (non-volatile)

• ROM (mask ROM): contents fixed at manufacture.
• PROM: programmable once by the user.
• EPROM: erasable with ultraviolet light, reprogrammable.
• EEPROM: erasable electrically, a byte at a time.
• Flash: electrically erasable in blocks; SSDs and firmware chips.

Chip organisation 2ᵏ × n

A chip "2ᵏ × n" (for example 4K × 8) holds 2ᵏ locations of n bits each:

• k address lines (4K = 2¹² → 12),
• n data lines (8),
• capacity 2ᵏ × n bits (4K × 8 = 32 Kb = 4 KB),
• a chip select (CS) input enables the chip, plus read/write control.

DRAM address multiplexing

DRAM cells sit in a square-ish array of rows and columns. The address is sent in two halves on the same pins: the row address (latched by RAS, row address strobe), then the column address (latched by CAS). A 16M × 1 DRAM (2²⁴ cells as 4096 × 4096) needs 24 address bits but only 12 address pins.

Refresh

Every row must be refreshed once per refresh period (say 64 ms). Refreshing one row takes about one memory cycle.

• Time spent refreshing per period = rows × time per row refresh.
• Refresh overhead = (rows × row-refresh time) / refresh period.

Example: 8,192 rows, 50 ns per row, 64 ms period: 8192 × 50 ns = 409.6 µs per 64 ms = 0.64%.

Refresh can be done in one burst (all rows back to back) or distributed (one row every period ÷ rows: 64 ms / 8192 = 7.8 µs).

Access time vs cycle time

Access time: from request to data available. Cycle time: minimum time between two successive accesses (for DRAM, longer than access time because the row must be restored).

4 · Visual

4K x 8 chip                         DRAM with multiplexed address (4096 x 4096 cells)

 A11..A0 --12--> +--------+           A11..A0 --12--> [row latch (RAS)] --> row decoder
                 |  4K x 8| --8--> D7..D0             [col latch (CAS)] --> column MUX
 CS, R/W ------> +--------+          24-bit address sent as 12 + 12 on the same pins

5 · Worked Examples

Example 1 Easy

How many address and data lines does a 64K × 16 chip have?

Solution

64K = 2¹⁶ → 16 address lines, 16 data lines.

Example 2 Medium

A DRAM has 4,096 rows; refreshing a row takes 100 ns; every row must be refreshed every 2 ms. What percentage of time goes to refresh?

Solution

4096 × 100 ns = 409.6 µs per 2 ms → 409.6 / 2000 = 20.48%.

Example 3 GATE

A 256M × 1 DRAM uses a square cell array and multiplexed row/column addresses. How many address pins does it need?

Solution

256M = 2²⁸ cells = 2¹⁴ × 2¹⁴ → 14 pins (row and column each 14 bits, sent one after the other).

6 · GATE Traps

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• SRAM needs no refresh; DRAM does.
• 2ᵏ × n: k address lines, n data lines; capacity in bits is 2ᵏ·n.
• Refresh overhead uses rows × per-row time, divided by the refresh period.
• Multiplexed DRAM addressing halves the address pins.

7 · Memory Hook

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"SRAM stays, DRAM decays." Static holds while powered; dynamic must be refreshed.

8 · Connect the Dots

You know the chips and their pins. Next: wiring many chips into one memory, wider words side by side, more words in rows selected by a decoder, and counting the chips.

9 · Self-Test

GATE format. Try every question before opening the vault.

Q1NAT1 markAddress lines

A chip is organised as 512K × 8. How many address lines?

Numerical answer: ________

Q2NAT2 marksRefresh overhead

A DRAM with 16,384 rows must refresh each row every 32 ms; a row refresh takes 40 ns. Percentage of time spent refreshing?

Numerical answer: ________

Q3MCQ1 markCell types

Which statement is correct?

• (A) SRAM cells use a capacitor and need refresh
• (B) SRAM is non-volatile
• (C) DRAM is denser and cheaper per bit than SRAM
• (D) DRAM is used for on-chip caches

Q4NAT2 marksMultiplexed pins

A 64M × 4 DRAM chip stores its 64M locations in a square array with multiplexed row/column addressing. How many address pins?

Numerical answer: ________

Q5MSQ2 marksROM family

Which can be erased and reprogrammed electrically?

• (A) PROM
• (B) Mask ROM
• (C) Flash
• (D) EEPROM

10 · Rule Card

• SRAM: flip-flop, fast, no refresh, caches. DRAM: capacitor, dense, cheap, refresh, main memory.
• ROM, PROM (once), EPROM (UV), EEPROM (byte, electrical), Flash (block, electrical).
• 2ᵏ × n chip: k address lines, n data lines, CS.
• DRAM refresh overhead = rows × row time / refresh period; multiplexed address pins = half the bits (square array).

11 · Concept Ledger

Unlocked in this lesson. From here on, these terms may be used.

SRAMDRAMrefreshvolatile vs non-volatileROM, PROM, EPROM, EEPROM, Flashchip organisation 2ᵏ × nchip select (CS)RAS/CAS address multiplexingrefresh overheadburst vs distributed refreshaccess time vs cycle time

12 · Answer Vault