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COA/Phase 6 · I/O: Interrupts & DMA

Chapter review LI-6.1 · Item 75 of 87

I/O basics

Read at your own pace. Try the questions before opening the answers.

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ACompressed recap

🧾

An I/O interface exposes data, status and control registers (ports). Memory-mapped I/O: ports in the memory space, ordinary LOAD/STORE, memory space reduced. Isolated I/O: separate space, IN/OUT, select line. Synchronous bus (clock) vs asynchronous (handshake); arbitration by daisy chain or central arbiter. Programmed I/O: CPU checks status and moves every word; polling fraction = polls/s × cycles per poll ÷ f; minimum polling rate = data rate ÷ bytes per poll; busy-waiting ties up the CPU for the whole transfer.

BMerged rule card

6.1.1 I/O devices, interfaces and ports; memory-mapped vs I/O-mapped I/O; buses

  • Interface registers (ports): data, status, control.
  • Memory-mapped: ports in memory space, LOAD/STORE, memory space reduced.
  • Isolated: separate space, IN/OUT, extra select line.
  • Synchronous bus: clock. Asynchronous: handshake. Arbitration: daisy chain or central.

6.1.2 Programmed I/O: polling, busy-waiting and its CPU cost

  • Programmed I/O: CPU checks status, moves each word; busy-waits.
  • Polling fraction = r × p / f; minimum r = data rate ÷ bytes per poll.
  • Busy-waiting occupies the CPU for the whole transfer.
  • I/O rates: decimal unless stated.

CInterleaved GATE-style questions

Q1NAT1 markSpace

24-bit address space; 1 MB is used for memory-mapped I/O. How many MB remain for memory?

Numerical answer: ________

Q2MCQ1 markInstructions

With memory-mapped I/O, a program reads a device's status register with:

  • (A) an interrupt
  • (B) an ordinary load instruction
  • (C) an IN instruction
  • (D) a DMA request

Q3NAT2 marksPolling

A 1 GHz CPU must poll a device that produces 2 MB/s (decimal) in 16-byte chunks; each poll costs 500 cycles. Percentage of CPU time?

Numerical answer: ________

Q4NAT2 marksPolling slow device

A keyboard is polled 100 times per second at 1,000 cycles per poll on a 200 MHz CPU. Percentage of CPU time?

Numerical answer: ________

Q5MSQ2 marksInterface

Which are true?

  • (A) Isolated I/O reduces the memory address space.
  • (B) A status register tells the CPU whether the device is ready.
  • (C) A daisy chain gives priority by position.
  • (D) Asynchronous buses use request/acknowledge handshakes.

Q6NAT1 markBusy-wait

A printer accepts a character every 2 ms; the CPU busy-waits. How many seconds does printing 3,000 characters tie up the CPU?

Numerical answer: ________

DAnswer Vault

Answer Vault

Try the questions first. Open when you are ready to check.

Q1 Answer: 151 mark

16 − 1.

Re-read: Lesson 6.1.1 — I/O devices, interfaces and ports; memory-mapped vs I/O-mapped I/O; buses

Q2 Answer: (B)1 mark

Ports are memory addresses.

  • (A) is wrong: Interrupts are signals from devices.
  • (C) is wrong: IN is for isolated I/O.
  • (D) is wrong: Not how a program reads a register.

Re-read: Lesson 6.1.1 — I/O devices, interfaces and ports; memory-mapped vs I/O-mapped I/O; buses

Q3 Answer: 6.252 marks

125,000 polls/s × 500 = 6.25×10⁷.

Re-read: Lesson 6.1.2 — Programmed I/O: polling, busy-waiting and its CPU cost

Q4 Answer: 0.052 marks

10⁵ / 2×10⁸.

Re-read: Lesson 6.1.2 — Programmed I/O: polling, busy-waiting and its CPU cost

Q5 Answer: (B) (C) (D)2 marks

Isolated I/O keeps memory space intact.

  • (A) is wrong: That is memory-mapped I/O.

Re-read: Lesson 6.1.1 — I/O devices, interfaces and ports; memory-mapped vs I/O-mapped I/O; buses

Q6 Answer: 61 mark

3000 × 2 ms.

Re-read: Lesson 6.1.2 — Programmed I/O: polling, busy-waiting and its CPU cost

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