Microprogrammed control: control memory, control words, microroutines, µPC

0 · Recall Warm-up

Answer from memory first. Answers are in the Answer Vault at the bottom.

• Hardwired: Zin for ADDreg, ADDmem, BR? from Lesson 3.1.2
• What does WMFC do to the step counter? from Lesson 3.1.1
• What are MAR and MDR for? from Lesson 2.2.1

1 · The Hook

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In 1951 Maurice Wilkes noticed that each row of a step table is just a row of 0s and 1s. Store each row as a word in a small, fast memory and read the rows out one by one. That memory replaces the logic network, and changing the instruction set becomes as easy as rewriting the memory. This is microprogrammed control.

2 · Predict First

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The single-bus datapath has 36 control signals (Lesson 3.1.1). If each step's signals are stored as one word, how wide is a word, and how many words does the ADD R1, (R3) routine (fetch included) use?

Make a guess in your head. The answer opens Section 3.

3 · Core Concept

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Predict First — the answer

36 bits per word (one bit per signal) and 7 words (3 fetch steps + 4 execute steps).

Vocabulary

• Control word (CW): the bit pattern of all control signals for one step.
• Microinstruction: a control word stored in memory (plus, in Chapter 3.2.3, sequencing fields).
• Microroutine: the sequence of microinstructions that performs one machine instruction.
• Microprogram: all microroutines together; it is firmware.
• Control memory (CM, control store): the ROM (or writable store) that holds the microprogram.
• µPC (microprogram counter): address of the next microinstruction.

How it runs

• The fetch microroutine sits at a fixed CM address (say 0). Every machine instruction starts there.
• At the end of the fetch, the opcode in IR goes through a starting-address generator (mapping logic or a small ROM) that loads µPC with the address of that instruction's microroutine.
• µPC normally increments after each step (sequential microinstructions).
• The routine's last microinstruction has End, which sends µPC back to the fetch routine.
• Conditional branches and WMFC need extra sequencing (Lesson 3.2.3).

Each step costs one CM read, so the clock must allow for the CM access time.

Control memory size

CM words = (fetch microinstructions, shared) + Σ (execute microinstructions of every instruction). CM bits = words × microinstruction width.

Example: fetch 3 words; 40 instructions averaging 5 execute steps; 36-bit horizontal words → (3 + 200) × 36 = 7,308 bits.

Hardwired vs microprogrammed (first look)

4 · Visual

Microprogrammed control: µPC walks through control memory; the opcode picks the starting address.

5 · Worked Examples

Example 1 Easy

A microroutine has 5 execute microinstructions; the shared fetch has 3. How many microinstructions run for one execution of that instruction?

Solution

3 + 5 = 8.

Example 2 Medium

A CPU has 64 instructions, each with a 6-step execute microroutine, plus a 4-step fetch routine. Horizontal microinstructions are 48 bits wide. Control memory size in bits?

Solution

Words = 4 + 64 × 6 = 388; bits = 388 × 48 = 18,624.

Example 3 GATE

Why can microprogrammed control be slower than hardwired control for the same datapath?

Solution

Every step needs a control memory read, and the clock period must include the CM access time. Hardwired signals come straight from gates.

6 · GATE Traps

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• The fetch routine is shared: store it once, not once per instruction.
• Microinstructions executed (per run) ≠ CM words (stored).
• The opcode does not index CM directly unless stated; a mapping gives the start address.
• A microprogram is firmware, not software the programmer writes.

7 · Memory Hook

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"Each row of the step table becomes a word in control memory." µPC reads the rows; the opcode picks where to start.

8 · Connect the Dots

This lesson stored the control words one bit per signal. Next: squeezing them, horizontal vs vertical microinstructions, and computing widths and control-memory sizes the way GATE asks.

9 · Self-Test

GATE format. Try every question before opening the vault.

Q1NAT1 markMicroinstructions run

A machine instruction's microroutine has 7 execute microinstructions; fetch takes 4. How many microinstructions run per execution of that instruction?

Numerical answer: ________

Q2NAT2 marksCM size

A CPU has 100 instructions, each with a 5-microinstruction execute routine, plus a 3-microinstruction fetch routine. Microinstructions are 40 bits wide. Control memory size in bits?

Numerical answer: ________

Q3MCQ1 markµPC

After the fetch microroutine, the µPC is loaded from:

• (A) the MAR
• (B) the stack
• (C) the PC
• (D) a starting-address generator driven by the opcode

Q4MSQ2 marksMicroprogrammed control

Which are true?

• (A) Microprogrammed control is typically faster than hardwired.
• (B) The fetch microroutine is shared by all instructions.
• (C) Each step needs a control memory read.
• (D) Changing the instruction set can be done by changing the control memory contents.

Q5NAT1 markWidth

A horizontal microinstruction stores one bit per control signal. A datapath has 52 control signals. Width in bits?

Numerical answer: ________

10 · Rule Card

• Control word = all signals of one step; microinstruction = stored control word (+ sequencing).
• Microroutine per instruction; fetch routine shared; µPC + starting-address generator; End → fetch.
• CM words = fetch + Σ execute steps; CM bits = words × width.
• Microprogrammed: flexible, slower, CISC-friendly.

11 · Concept Ledger

Unlocked in this lesson. From here on, these terms may be used.

control wordmicroinstructionmicroroutinemicroprogram (firmware)control memory (control store)µPCstarting-address generator (mapping)CM size

12 · Answer Vault