DMA: the controller, burst mode, cycle stealing, transparent mode; CPU time lost

0 · Recall Warm-up

Answer from memory first. Answers are in the Answer Vault at the bottom.

• Gain of interrupt mode over busy-waiting? from Lesson 6.2.2
• What does a vectored interrupt supply? from Lesson 6.2.1
• Block fetch time with k-way low-order interleaving? from Lesson 4.1.5

1 · The Hook

🎣

A disk transferring 10 MB/s would interrupt the CPU hundreds of thousands of times a second. Direct memory access (DMA) hands the whole job to a small controller: the CPU says "move 20 KB from the disk to address X" and gets one interrupt when it is done. GATE asks how much CPU time is left over, and how often the DMA controller must take the bus.

2 · Predict First

🤔

A disk delivers 10 MB/s (decimal) by DMA in 20 KB (20,000-byte) blocks. The 600 MHz CPU spends 300 cycles starting each block and 900 cycles finishing it. What percentage of the CPU's time does this cost?

Make a guess in your head. The answer opens Section 3.

3 · Core Concept

💡

Predict First — the answer

One block takes 20,000 / 10⁷ = 2 ms to arrive. CPU work per block: 1,200 cycles = 2 µs. 2 µs / 2 ms = 0.1%.

How DMA works

• The CPU programs the DMA controller: memory start address, word (byte) count, direction, device.
• The controller asks for the bus (bus request / HOLD); the CPU grants it (bus grant / HLDA) at the end of a bus cycle.
• The controller moves data directly between the device and memory, updating the address and count registers.
• When the count reaches zero, it interrupts the CPU (one interrupt per block).

The CPU keeps executing during the transfer except when it needs the bus that DMA is using.

Transfer modes

• Burst (block) mode: the controller keeps the bus for the whole block; the CPU cannot access memory during that time. Fastest transfer.
• Cycle stealing: the controller takes the bus for one word at a time, stealing one bus cycle now and then; the CPU is slowed a little but never stopped for long.
• Transparent (hidden) mode: the controller uses the bus only in cycles when the CPU does not need it: no slowdown, slowest transfer.

CPU cost formulas

• Setup/completion overhead: fraction = (CPU time per block) ÷ (time for the device to deliver a block).
• Cycle stealing: fraction of bus cycles lost = (words per second × cycles stolen per word) ÷ (bus cycles per second).
• Burst mode with a device that prepares data first: if the device needs X to prepare a block and the bus transfer takes Y, the CPU is blocked from memory for Y / (X + Y) of the time.

DMA count register limit

A k-bit count register allows at most 2ᵏ units per DMA operation. Transferring a file of S units needs at least ⌈S / 2ᵏ⌉ DMA operations (times the controller takes control of the bus in burst mode).

Example: 16-bit byte count, file of 10,000 KB = 10,240,000 bytes: ⌈10,240,000 / 65,536⌉ = ⌈156.25⌉ = 157.

4 · Visual

DMA: the CPU sets up the transfer; the controller moves the block and interrupts once at the end.

5 · Worked Examples

Example 1 Easy

A 1 MB/s (decimal) device uses cycle stealing with 4-byte words; each word steals one bus cycle; the bus runs at 100 MHz. Fraction of bus cycles stolen?

Solution

250,000 words/s ÷ 10⁸ cycles/s = 0.25%.

Example 2 Medium

In burst mode, a device takes 2 ms to fill its buffer (X) and the DMA transfer of the buffer to memory takes 20 µs (Y). Percentage of time the CPU is blocked from memory?

Solution

20 / (2000 + 20) ≈ 0.99%.

Example 3 GATE

A DMA controller has a 16-bit byte-count register. How many times must it take control of the bus (burst mode) to move a file of 29,154 KB from disk to byte-addressable memory?

Solution

29,154 × 1,024 = 29,853,696 bytes; ÷ 65,536 = 455.5 → 456.

6 · GATE Traps

⚠️

• One interrupt per block, not per word.
• Cycle stealing slows the CPU only when it needs the bus that cycle.
• The count register limits units per DMA operation: round up.
• In DMA problems rates like MB/s are usually decimal; file sizes in KB are usually binary (1,024). Read the question.

7 · Memory Hook

🧠

"CPU sets it up, DMA moves it, one interrupt says done." Burst = fast but blocks; stealing = a cycle at a time; transparent = only when free.

8 · Connect the Dots

Phase 6 is complete, and with it the whole GATE COA syllabus: instructions and addressing, ALU and datapath, control unit, memory and cache, pipelining, and I/O. Phase 7 merges every rule card, drills mixed practice and GATE patterns, and ends with the graded final test.

9 · Self-Test

GATE format. Try every question before opening the vault.

Q1NAT2 marksSetup overhead

A disk delivers 8 MB/s (decimal) by DMA in 16 KB (16,000-byte) blocks. A 1 GHz CPU spends 1,000 cycles to set up and 1,000 to finish each block. Percentage of CPU time?

Numerical answer: ________

Q2NAT2 marksCycle stealing

A 2 MB/s (decimal) device uses cycle stealing, 2-byte words, one stolen bus cycle per word, bus at 50 MHz. Percentage of bus cycles stolen?

Numerical answer: ________

Q3NAT2 marksBurst blocking

Burst mode: the device prepares a block in 4 ms, the DMA transfer takes 40 µs. Percentage of time the CPU is blocked (2 decimals)?

Numerical answer: ________

Q4NAT2 marksCount register

A DMA controller has a 12-bit word count register; words are 4 bytes. Minimum number of DMA operations to move 1 MB (2²⁰ bytes)?

Numerical answer: ________

Q5MSQ2 marksDMA facts

Which are true?

• (A) In transparent mode the CPU is not slowed down.
• (B) The DMA controller transfers data between the device and memory without the CPU moving each word.
• (C) DMA needs one interrupt per word.
• (D) In burst mode the CPU cannot use the bus until the block is done.

10 · Rule Card

• DMA: CPU programs address, count, direction; controller requests bus (HOLD), gets grant (HLDA), transfers, interrupts at the end.
• Burst (block), cycle stealing (word at a time), transparent (idle cycles only).
• Overhead fraction = CPU time per block ÷ block delivery time. Cycle stealing = stolen cycles/s ÷ bus cycles/s. Burst blocking = Y/(X + Y).
• k-bit count → ⌈S / 2ᵏ⌉ DMA operations.

11 · Concept Ledger

Unlocked in this lesson. From here on, these terms may be used.

direct memory access (DMA)DMA controller (address, count registers)bus request/grant (HOLD/HLDA)burst (block) modecycle stealingtransparent (hidden) modeDMA CPU overheadcount-register limit

12 · Answer Vault