Interrupts: the interrupt cycle, ISR, context saving, vectored interrupts, priority and daisy chain

0 · Recall Warm-up

Answer from memory first. Answers are in the Answer Vault at the bottom.

• Polling fraction formula? from Lesson 6.1.2
• What does CALL push? from Lesson 1.3.2
• When in the instruction cycle does the CPU check for device requests? from Lesson 1.1.1

1 · The Hook

🎣

Instead of the CPU asking "ready yet?" thousands of times, let the device tap the CPU on the shoulder when it is ready. The CPU stops what it is doing, runs a short routine for the device, then resumes exactly where it was. Making "exactly where it was" work is the whole mechanism, and GATE asks which address gets saved.

2 · Predict First

🤔

A program runs at addresses 1000 onward (byte-addressable). Instructions: I1 at 1000 (8 bytes), I2 (4 bytes), I3 (4 bytes), I4 (8 bytes). A device interrupts while I3 is executing. What return address is saved?

Make a guess in your head. The answer opens Section 3.

3 · Core Concept

💡

Predict First — the answer

I2 starts at 1008, I3 at 1012, I4 at 1016. I3 finishes first, then the CPU saves 1016, the address of the next instruction.

The interrupt sequence

• The device raises INTR (interrupt request).

• The CPU finishes the current instruction (interrupts are checked at the end of the instruction cycle).

• If interrupts are enabled (IE flag in the PSW), the CPU acknowledges (INTA) and:

• saves the PC (the next instruction's address) and usually the PSW (flags) on the stack,

• disables further interrupts (or raises the priority level),

• loads the PC with the address of the interrupt service routine (ISR).

• The ISR saves any registers it uses, serves the device (reads the data register), restores registers.

• RTI (return from interrupt) pops the PSW and PC: the program continues as if nothing happened.

An interrupt is like an unplanned CALL, triggered by hardware between two instructions.

Finding the ISR

• Vectored interrupts: the device supplies a vector (a small number) during acknowledge; the CPU reads the ISR address from an interrupt vector table: entry address = table base + vector × entry size.
• Non-vectored: one fixed ISR address; the ISR polls the devices' status registers to find who interrupted (software poll).

Several devices: priority

• Daisy chain: INTA travels from the CPU through the devices in a line; the first requesting device on the line keeps it and puts its vector on the bus. Priority = position (nearest the CPU wins).
• Separate request lines + priority encoder: the highest-priority active request wins.
• Masking: individual interrupts can be disabled with a mask register. A non-maskable interrupt (NMI) cannot be disabled (power failure, hardware error).
• Nested interrupts: a higher-priority device may interrupt a lower-priority ISR, if the ISR re-enables interrupts.

Interrupt latency

Time from the request to the start of the ISR: finish the current instruction + save state + fetch the vector.

4 · Visual

Main program                         ISR
 1000 I1 (8 B)
 1008 I2                       +--> save registers
 1012 I3  <- INTR arrives      |    read device data
        I3 completes           |    restore registers
        push PSW, push 1016 ---+    RTI: pop 1016, pop PSW
 1016 I4  <--------------------------------+

Daisy chain:  CPU --INTA--> [Dev A] --> [Dev B] --> [Dev C]
              first requesting device on the line takes INTA: A beats B beats C

5 · Worked Examples

Example 1 Easy

A vector table starts at address 0; each entry is 4 bytes. Device vector 9: where is its ISR address stored?

Solution

0 + 9 × 4 = 36.

Example 2 Medium

Three devices on a daisy chain in order A (nearest the CPU), B, C. B and C request at the same time. Who is served first?

Solution

B, the one nearer the CPU on the chain.

Example 3 GATE

Word-addressable memory, instructions of 1 or 2 words: MOV R1, (3000) 2 words at 1000; MOV R2, (R3) 1 word; ADD R2, R1 1 word; MOV (R3), R2 1 word; INC R3 1 word. An interrupt arrives during INC R3. What return address is pushed?

Solution

Addresses: 1000 (2 words), 1002, 1003, 1004, INC at 1005. After INC completes, the next instruction is at 1006: that is pushed.

6 · GATE Traps

⚠️

• The current instruction completes; the saved PC is the next instruction.
• Vector entry = base + vector × entry size.
• In a daisy chain, priority is position, not device speed.
• NMI cannot be masked.

7 · Memory Hook

🧠

"Finish, save, jump, serve, return."

8 · Connect the Dots

This lesson built the interrupt mechanism. Next: what it costs per transfer, and when interrupt-driven I/O beats polling by how much.

9 · Self-Test

GATE format. Try every question before opening the vault.

Q1NAT1 markReturn address

Byte-addressable; a program starts at 2000 with instructions of 4, 8, 4, 4 and 8 bytes. An interrupt arrives during the 4th instruction. What return address is saved?

Numerical answer: ________

Q2NAT1 markVector table

A vector table at 0x400 (1024) with 8-byte entries. Where is the ISR address for vector 12 (decimal address)?

Numerical answer: ________

Q3MCQ1 markDaisy chain

In a daisy-chain priority scheme:

• (A) priority rotates after each interrupt
• (B) all devices have equal priority
• (C) the device farthest from the CPU has the highest priority
• (D) the device nearest the CPU on the acknowledge line has the highest priority

Q4MSQ2 marksInterrupt steps

Which happen when an enabled interrupt is accepted?

• (A) The PC is saved.
• (B) The current instruction is completed first.
• (C) Interrupts are usually disabled while the ISR starts.
• (D) The interrupted instruction is restarted from its first step after the ISR.

Q5MCQ1 markNon-vectored

In a non-vectored interrupt system, the ISR finds which device interrupted by:

• (A) the daisy-chain position automatically
• (B) DMA
• (C) reading the vector supplied by the device
• (D) polling the devices' status registers

10 · Rule Card

• Interrupt: finish current instruction → (if enabled) save PC (next instruction) and PSW → disable → ISR → RTI.
• Vectored: ISR address at table base + vector × entry size. Non-vectored: ISR polls devices.
• Daisy chain: priority by position. Mask register; NMI unmaskable; nesting by priority.

11 · Concept Ledger

Unlocked in this lesson. From here on, these terms may be used.

interrupt request (INTR)interrupt acknowledge (INTA)interrupt enable flaginterrupt service routine (ISR)return from interrupt (RTI)saving PC and PSWvectored interruptinterrupt vector tablenon-vectored interrupt (software poll)daisy-chain prioritypriority encoderinterrupt maskingnon-maskable interrupt (NMI)nested interruptsinterrupt latency

12 · Answer Vault