Thirty questions in GATE format covering all phases (15 one-mark, 15 two-mark; 45 marks). Set a 90-minute timer, work on paper, and enter your answers in the boxes. For MSQ tick all correct options; for NAT enter a number. Then press Submit answers: the page scores you with GATE negative marking, shows topic-wise accuracy, lists the questions you got wrong and the lessons to re-read. The full key is at the very end of these notes.
Conventions: byte-addressable memory unless stated; K = 2¹⁰ for sizes; decimal rates; 5-stage pipeline IF ID EX MEM WB with a split-cycle register file.
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30 questions · 45 marks · 90 minutes. Negative marking on MCQ only: −1/3 mark for a wrong 1-mark MCQ, −2/3 for a wrong 2-mark MCQ. No negative marking for MSQ or NAT; MSQ has no partial credit.
Q1MCQ1 markStored program
A machine with separate memories and paths for instructions and data is called:
- (A) von Neumann
- (B) Harvard
- (C) accumulator machine
- (D) stack machine
Q2NAT1 markAddress bits
A byte-addressable memory holds 128 MB. How many address bits?
Your answer:
Q3MCQ1 markEndianness
0xA1B2C3D4 is stored big-endian at address 100. Which byte is at address 102?
- (A) 0xD4
- (B) 0xA1
- (C) 0xC3
- (D) 0xB2
Q4NAT1 markInstruction fields
A 32-bit instruction has an opcode for 80 operations and three register fields for 32 registers. How many bits remain for an immediate?
Your answer:
Q5MCQ1 markAddressing mode
t = *p; where the pointer p is stored in a memory word (not a register). The natural mode is:
- (A) register indirect
- (B) memory indirect
- (C) PC-relative
- (D) immediate
Q6NAT1 markALU control
An ALU supports 14 operations with an encoded select field. Bits needed?
Your answer:
Q7MCQ1 markCPU registers
Which register supplies the address to memory?
- (A) PC
- (B) IR
- (C) MDR
- (D) MAR
Q8MCQ1 markControl unit
Compared with hardwired control, microprogrammed control is:
- (A) faster and harder to modify
- (B) slower and easier to modify
- (C) slower and harder to modify
- (D) faster and easier to modify
Q9NAT1 markHit ratio
9,700 of 10,000 memory accesses hit in the cache. Hit ratio?
Your answer:
Q10MCQ1 markMemory cells
Main memory is usually DRAM rather than SRAM because DRAM:
- (A) is faster
- (B) is denser and cheaper per bit
- (C) is non-volatile
- (D) needs no refresh
Q11NAT1 markDirect mapping
16-bit addresses, a 512-byte direct-mapped cache with 32-byte blocks. Which line does address 0x5A7C map to?
Your answer:
Q12MSQ1 markWrite policies
Which are true of a write-back cache?
- (A) Every write hit also writes main memory.
- (B) A dirty line is written to memory when it is evicted.
- (C) It needs a dirty bit per line.
- (D) It is usually paired with write-allocate.
Q13NAT1 markPipeline cycles
A 6-stage pipeline runs 100 instructions without stalls. Cycles?
Your answer:
Q14MSQ1 markDependences
I1: ADD R1, R2, R3 and I2: MUL R1, R1, R4. Which dependences exist from I1 to I2?
- (A) WAR on R1
- (B) WAW on R1
- (C) RAW on R2
- (D) RAW on R1
Q15MCQ1 markDMA modes
In cycle-stealing DMA:
- (A) the controller uses only cycles the CPU does not need
- (B) the CPU moves each word
- (C) the controller takes the bus for one word at a time
- (D) the controller holds the bus for the whole block
Q16NAT2 marksCPU time
Mix: 50% ALU (1 cycle), 30% loads/stores (3 cycles), 20% branches (2 cycles). 2 × 10⁹ instructions at 1.2 GHz. Time in seconds?
Your answer:
Q17NAT2 marksExpanding opcode
16-bit instructions, 4-bit register fields: 12 three-register and 50 two-register instructions. Maximum one-register instructions?
Your answer:
Q18NAT2 marksProgram cycles
MOV R1, #0 (1) · MOV R2, #30 (1) · LOOP: ADD R1, R1, R2 (1) · SUB R2, R2, #1 (1) · BNZ R2, LOOP (2) · HALT (1). Total cycles?
Your answer:
Q19NAT2 marksBooth
Booth's algorithm with the 8-bit multiplier 1001 1001: total additions plus subtractions?
Your answer:
Q20NAT2 marksSingle-bus steps
Single bus (fetch 3 steps): total control steps for ADD R1, (R3), then SUB R4, R5, R6, then a conditional branch whose condition is false (ends in step 4)?
Your answer:
Q21NAT2 marksMicroinstruction
Vertical control field with mutually exclusive groups of 5, 9, 14 and 3 signals (each may be idle); a MUX selects one of 6 conditions; control memory of 1,024 words. Microinstruction width?
Your answer:
Q22NAT2 marksThree-level AMAT
L1 1 ns (h = 0.9); L2 12 ns (local h = 0.85); memory 150 ns. Hierarchical AMAT (ns)?
Your answer:
Q23NAT2 marksChips
How many 128K × 4 chips make a 1 MB byte-addressable memory?
Your answer:
Q24NAT2 marksTag directory
4-way, 256 KB, 64-byte blocks, 32-bit addresses; V, D and 2 LRU bits per line. Tag directory bits?
Your answer:
Q25NAT2 marksCache trace
An 8-line 4-way set-associative LRU cache receives blocks 1, 5, 9, 1, 5, 13, 1, 9. Number of misses?
Your answer:
Q26NAT2 marksCPI with misses
2 GHz CPU, base CPI 1.1, 1.3 memory accesses per instruction, miss rate 2.5%. Miss penalty: 40 ns latency plus a 64-byte block over an 8-byte bus at 5 ns per transfer. Effective CPI?
Your answer:
Q27NAT2 marksForwarding
With full forwarding: ADD R1, R2, R3 · LOAD R4, 0(R1) · ADD R5, R4, R1 · STORE R5, 0(R1) · ADD R6, R5, R4. Cycles?
Your answer:
Q28NAT2 marksBranch timing
5-stage pipeline with stage delays 4, 6, 5, 6, 3 ns and 1 ns latches. 9 instructions; I3 is a branch taken to I7, resolved at the end of stage 3; the pipeline stalls until then. Total time (ns)?
Your answer:
Q29NAT2 marksArray misses
int A[128][128] (4 bytes) at address 0; 16 KB direct-mapped cache with 32-byte blocks; column-wise traversal. Number of misses?
Your answer:
Q30NAT2 marksDMA
DMA from a 10 MB/s (decimal) device in 40,000-byte blocks; the 1 GHz CPU spends 8,000 cycles per block. Percentage of CPU time?
Your answer:
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