Microprogram sequencing: next-address field, conditional branches; hardwired vs microprogrammed

0 · Recall Warm-up

Answer from memory first. Answers are in the Answer Vault at the bottom.

• Field width for 12 mutually exclusive signals that may be idle? from Lesson 3.2.2
• What sends µPC back to the fetch routine? from Lesson 3.2.1
• Hardwired control: what is each signal's equation? from Lesson 3.1.2

1 · The Hook

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µPC + 1 handles straight-line microroutines. But a conditional branch instruction must jump to different microinstructions depending on a flag, and WMFC must loop until memory is ready. So microinstructions carry sequencing fields. GATE has asked for their widths more than once.

2 · Predict First

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A microinstruction is 26 bits: a 13-bit control field, a field that selects one of 8 status bits to test, and a next-address field. How wide is each of the last two fields, and how many words can the control memory have?

Make a guess in your head. The answer opens Section 3.

3 · Core Concept

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Predict First — the answer

Condition select: log₂ 8 = 3 bits. Next address: 26 − 13 − 3 = 10 bits → control memory of 2¹⁰ = 1,024 words.

Ways to choose the next microinstruction

• Sequential: µPC ← µPC + 1.
• Branch (unconditional or conditional): µPC ← next-address field, if the selected condition is true.
• Mapping: after the fetch, µPC ← start address from the opcode.
• Return to fetch (End): µPC ← fetch address.

Microinstruction with explicit sequencing

• Condition select chooses which status signal (Z, N, C, V, MFC, interrupt request, "always", "never" …) a MUX tests. Width = ⌈log₂(number of inputs to that MUX)⌉.
• Next address holds the branch target in CM. Width = ⌈log₂(CM words)⌉; conversely CM words = 2^(next-address width).
• If the tested condition is true, µPC ← next address; otherwise µPC ← µPC + 1.

Width: W = control bits + condition-select bits + next-address bits.

Example: WMFC as a microprogram loop

A microinstruction with condition "MFC = 0" and next address = itself keeps re-executing until memory finishes.

Explicit vs implicit next address

Storing a next address in every microinstruction costs bits; using µPC + 1 by default and branching only when needed saves them. Some designs put a next address in every word so that microinstructions can be placed anywhere.

Nanoprogramming (two-level control store)

Many microinstructions repeat the same control word. Store each distinct control word once in a nanomemory, and let each microinstruction hold only a short pointer to it.

• One level: N × W bits.
• Two levels: N × ⌈log₂ D⌉ + D × W bits (D distinct control words).
• Example: N = 2,048 microinstructions, W = 200 bits, D = 256 distinct: one level 409,600 bits; two levels 2,048 × 8 + 256 × 200 = 16,384 + 51,200 = 67,584 bits.

Hardwired vs microprogrammed: the full comparison

4 · Visual

Sequencing: if the selected condition is true, µPC takes the next-address field; otherwise µPC + 1.

5 · Worked Examples

Example 1 Easy

A control memory has 4,096 words. How wide must the next-address field be?

Solution

log₂ 4096 = 12 bits.

Example 2 Medium

Microinstructions are 32 bits: control field 18 bits, condition select chooses among 16 conditions. Next-address width and maximum CM words?

Solution

Select 4 bits; next address 32 − 18 − 4 = 10 bits; CM up to 1,024 words.

Example 3 GATE

Horizontal control field for 40 signals; a MUX selects among 6 conditions; the CM holds 500 microinstructions. Minimum microinstruction width?

Solution

40 + ⌈log₂ 6⌉ + ⌈log₂ 500⌉ = 40 + 3 + 9 = 52 bits.

6 · GATE Traps

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• CM words = 2^(next-address bits); next-address bits = ⌈log₂ words⌉.
• Condition select width counts the MUX inputs (status bits), not the number of instructions.
• Nanoprogramming saves space only when distinct control words D are few compared with N.
• "Hardwired = fast, microprogrammed = flexible" is the one-line comparison.

7 · Memory Hook

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"Control + condition + next address = width." Next-address bits ↔ log₂ of control memory size.

8 · Connect the Dots

Phase 3 is complete: the control unit, hardwired and microprogrammed, with every width and size formula. Phase 4 turns to memory: why a hierarchy, chips, interfacing and, above all, caches.

9 · Self-Test

GATE format. Try every question before opening the vault.

Q1NAT1 markNext address

A microinstruction is 30 bits: 16-bit control field, 4-bit condition select. Maximum number of control-memory words?

Numerical answer: ________

Q2NAT2 marksWidth

A horizontal control field of 54 signals, a MUX that selects one of 12 status bits, and a control memory of 2,000 words. Minimum microinstruction width?

Numerical answer: ________

Q3NAT2 marksNanoprogramming

N = 1,024 microinstructions of W = 120 control bits, with D = 64 distinct control words. Total bits with a two-level (nano) store?

Numerical answer: ________

Q4MCQ1 markComparison

Which is an advantage of microprogrammed over hardwired control?

• (A) No memory needed
• (B) Fewer control signals
• (C) Easier to modify and extend the instruction set
• (D) Higher speed

Q5MSQ2 marksSequencing

Which are ways a microprogrammed control unit chooses the next microinstruction?

• (A) µPC + 1
• (B) Mapping from the opcode after the fetch
• (C) Next-address field when a selected condition is true
• (D) Reading the main-memory PC

10 · Rule Card

• Next microinstruction: µPC + 1; branch to next-address field if condition true; opcode mapping; End → fetch.
• Width = control bits + ⌈log₂ #conditions⌉ + ⌈log₂ CM words⌉; CM words = 2^(next-address bits).
• Nanoprogramming: N·⌈log₂ D⌉ + D·W vs N·W.
• Hardwired: fast, rigid, RISC. Microprogrammed: flexible, slower, CISC.

11 · Concept Ledger

Unlocked in this lesson. From here on, these terms may be used.

sequencingcondition select fieldnext-address fieldstatus-bit MUXWMFC loop in microcodenanoprogramming (two-level control store)hardwired vs microprogrammed comparison

12 · Answer Vault