Speedup, efficiency, throughput; unequal stages, latch delay, splitting stages

0 · Recall Warm-up

Answer from memory first. Answers are in the Answer Vault at the bottom.

• Cycles for n instructions in a k-stage pipeline? from Lesson 5.1.1
• Cycle time with unequal stages? from Lesson 5.1.1
• Amdahl's law? from Lesson 0.1.2

1 · The Hook

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"A 4-stage pipeline gives a 4× speedup" is only true in the limit, with perfectly balanced stages and no latch delay. Real stages are unequal and latches cost time, so GATE asks for the actual speedup, and what happens if you split the slowest stage in two.

2 · Predict First

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Stages take 150, 120, 160 and 140 ns; latches add 5 ns. For a very long program, what is the speedup over the non-pipelined design?

Make a guess in your head. The answer opens Section 3.

3 · Core Concept

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Predict First — the answer

Non-pipelined per instruction: 570 ns. Pipelined: one instruction per 165 ns. Speedup → 570 / 165 ≈ 3.45, not 4.

Speedup

Speedup = non-pipelined time ÷ pipelined time.

• Equal stages of τ, no latch delay: S = n·k·τ / ((k + n − 1)τ) = nk / (k + n − 1) → k as n → ∞.
• Unequal stages t₁ … t_k, latch d: S = n·Σtᵢ / ((k + n − 1)(max tᵢ + d)) → Σtᵢ / (max tᵢ + d) for large n.

Predict numbers for 1,000 instructions: pipelined (4 + 999) × 165 = 165,495 ns; non-pipelined 1000 × 570 = 570,000 ns; speedup ≈ 3.44.

Efficiency and throughput

• Efficiency = speedup ÷ k = fraction of stage-slots doing useful work. Equal stages: n / (k + n − 1).
• Throughput = instructions completed per unit time = n / ((k + n − 1)τ) → 1/τ for large n.

Example: k = 5, n = 20, τ = 10 ns: time = 24 × 10 = 240 ns; speedup (vs 5τ per instruction) = 20 × 50 / 240 ≈ 4.17; efficiency ≈ 0.83; throughput = 20 / 240 ns ≈ 83.3 million instructions per second.

Splitting the slowest stage

Split a slow stage into two halves: the cycle shrinks to the new maximum, but k grows by one (more fill time and one more latch).

Predict pipeline with the 160 ns stage split into two 80 ns stages: stages 150, 120, 80, 80, 140; τ = 150 + 5 = 155 ns; k = 5. For 1,000 instructions: (5 + 999) × 155 = 155,620 ns, faster than 165,495 ns. Splitting helps only the stage that is the maximum; here 150 is now the bottleneck.

Balancing

The ideal is balanced stages: equal delays, so no stage idles. Unbalanced stages waste the difference between each stage and the slowest one every cycle.

4 · Visual

5 · Worked Examples

Example 1 Easy

A balanced 6-stage pipeline (no latch delay) runs 300 instructions. Speedup over non-pipelined?

Solution

300 × 6 / (6 + 299) = 1800 / 305 ≈ 5.9.

Example 2 Medium

Same pipeline. Efficiency?

Solution

300 / 305 ≈ 0.984.

Example 3 GATE

Stages 10, 15, 12, 8 ns; latch 1 ns. Large-n speedup over the non-pipelined design?

Solution

Σ = 45 ns; τ = 16 ns → 45 / 16 ≈ 2.81.

6 · GATE Traps

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• The speedup limit k needs balanced stages and no latch overhead.
• With unequal stages the large-n speedup is Σtᵢ / (max tᵢ + d).
• Splitting a stage raises k: recompute both τ and the fill term.
• Throughput tends to 1/τ, not k/τ.

7 · Memory Hook

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"Speedup = sum over max." For long programs: Σ stage delays ÷ (slowest stage + latch).

8 · Connect the Dots

Lesson 5.1.1 timed a pipeline; this lesson compared it with no pipeline and tuned the stages. Next: the real 5-stage RISC pipeline, IF ID EX MEM WB, which every hazard question uses.

9 · Self-Test

GATE format. Try every question before opening the vault.

Q1NAT2 marksTime

Stages 25, 30, 20, 35 ns; latch 5 ns. Time (ns) for 500 instructions?

Numerical answer: ________

Q2NAT2 marksSpeedup

Same pipeline. Speedup over non-pipelined for 500 instructions (2 decimals)?

Numerical answer: ________

Q3NAT1 markEfficiency

A balanced 4-stage pipeline runs 97 instructions. Efficiency (as a decimal)?

Numerical answer: ________

Q4NAT2 marksSplitting

Stages 40, 60, 50 ns, latch 2 ns. The 60 ns stage is split into two 30 ns stages. New time (ns) for 100 instructions?

Numerical answer: ________

Q5MSQ2 marksFacts

Which are true?

• (A) Splitting any stage always reduces the cycle time.
• (B) A balanced k-stage pipeline approaches a speedup of k for long programs.
• (C) Efficiency = speedup ÷ number of stages.
• (D) Latch delay reduces the achievable speedup.

10 · Rule Card

• Speedup = T_nonpipe / T_pipe; balanced: nk/(k+n−1) → k.
• Unequal: large-n speedup = Σtᵢ / (max tᵢ + d).
• Efficiency = speedup/k = n/(k+n−1) (balanced). Throughput → 1/τ.
• Splitting the bottleneck: new τ = new max + d, k + 1 stages.

11 · Concept Ledger

Unlocked in this lesson. From here on, these terms may be used.

pipeline speedupspeedup limit kefficiencythroughputbalanced vs unbalanced stagessplitting a stage

12 · Answer Vault