5.1.3 The 5-stage RISC pipeline IF ID EX MEM WB; space–time diagrams

0 · Recall Warm-up

Answer from memory first. Answers are in the Answer Vault at the bottom.

Large-n speedup with stages t₁…t_k and latch d? from Lesson 5.1.2
Pipeline cycles for n instructions, k stages? from Lesson 5.1.1
Why can a Harvard machine fetch and read data in the same cycle? from Lesson 0.1.1

1 · The Hook

🎣

GATE pipeline questions almost always use one particular pipeline, the classic 5-stage RISC design: IF, ID, EX, MEM, WB. Knowing exactly what each stage does, and when a register is written and read, decides every hazard answer in Chapter 5.2.

2 · Predict First

🤔

In cycle 5 of a 5-stage pipeline that started I1 in cycle 1 and one new instruction per cycle, which instruction is in which stage?

Make a guess in your head. The answer opens Section 3.

3 · Core Concept

💡

Predict First — the answer

I1 in WB, I2 in MEM, I3 in EX, I4 in ID, I5 in IF: the pipeline is full.

The five stages

Stage	Work
IF (instruction fetch)	read the instruction at PC from the instruction cache; PC ← PC + 4
ID (instruction decode)	decode; read source registers from the register file; sign-extend the immediate
EX (execute)	ALU operation, or address calculation (base + offset) for loads/stores, or branch comparison and target
MEM (memory)	loads read the data cache; stores write it; other instructions pass through
WB (write back)	write the result register (ALU result or loaded value)

Pipeline registers: IF/ID, ID/EX, EX/MEM, MEM/WB.

Who uses what

Load: all five stages (address in EX, data in MEM, register write in WB).
Store: address in EX, write in MEM; no register write in WB.
ALU instruction: result in EX, passes through MEM, written in WB.
Branch: compare and compute the target in EX (some designs move this to ID).

Two conventions that matter

Separate instruction and data caches, so IF and MEM never compete for one memory in the same cycle.
Register file written in the first half of a cycle and read in the second half: an instruction in WB and a later instruction in ID can share a cycle, and the reader gets the new value.

Ideal CPI = 1: one instruction completes per cycle once the pipeline is full.

4 · Visual

Instr	1	2	3	4	5	6	7	8	9
I1	IF	ID	EX	MEM	WB
I2		IF	ID	EX	MEM	WB
I3			IF	ID	EX	MEM	WB
I4				IF	ID	EX	MEM	WB
I5					IF	ID	EX	MEM	WB

One cycle, split:   |  first half: WB writes register  |  second half: ID reads registers  |

5 · Worked Examples

Example 1 Easy

In which stage does a load compute its memory address?

Solution

EX (base register + offset in the ALU).

Example 2 Medium

How many cycles do 12 instructions take in the ideal 5-stage pipeline?

Solution

5 + 12 − 1 = 16.

Example 3 GATE

Without separate instruction and data caches, which two stages would compete for memory in the same cycle?

Solution

IF (fetching a later instruction) and MEM (a load or store of an earlier one).

6 · GATE Traps

⚠️

Registers are read in ID, written in WB.
With the split-cycle register file, WB and ID in the same cycle is fine.
Stores do nothing in WB; ALU instructions do nothing in MEM.
Ideal CPI is 1, not 1/5.

7 · Memory Hook

🧠

"I-F, I-D, EX, MEM, WB: fetch, read, compute, memory, write." Write early, read late in a cycle.

8 · Connect the Dots

Chapter 5.1 is complete: pipeline timing and the 5-stage design. Chapter 5.2 is about hazards: the situations where the next instruction cannot proceed in its cycle, starting with competition for hardware.

9 · Self-Test

GATE format. Try every question before opening the vault.

Q1MCQ1 markRegister read

In the classic 5-stage pipeline, source registers are read in:

(A) ID
(B) WB
(C) IF
(D) EX

Q2NAT1 markIdeal cycles

The ideal 5-stage pipeline runs 1,000 instructions. Total cycles?

Numerical answer: ________

Q3MCQ1 markStage contents

In cycle 7 (I1 started in cycle 1, one instruction per cycle, no stalls), which instruction is in EX?

(A) I4
(B) I3
(C) I6
(D) I5

Q4MSQ2 marksStore

Which stages does a store use for real work?

(A) IF
(B) EX (address)
(C) MEM (write)
(D) WB (register write)

Q5NAT1 markIdeal CPI

What is the ideal CPI of the 5-stage pipeline?

Numerical answer: ________

10 · Rule Card

IF: fetch, PC + 4. ID: decode, read registers. EX: ALU / address / branch. MEM: load/store. WB: write register.
Separate I- and D-caches; register file write first half, read second half.
Instruction i (no stalls) is in stage s at cycle i + s − 1.
Ideal CPI = 1.

11 · Concept Ledger

Unlocked in this lesson. From here on, these terms may be used.

IF, ID, EX, MEM, WBpipeline registers IF/ID, ID/EX, EX/MEM, MEM/WBsplit-cycle register fileseparate instruction and data cachesideal CPI = 1

12 · Answer Vault

Answer Vault

Try the questions first. Open when you are ready to check.

Recall Warm-up

Σtᵢ / (max tᵢ + d).
k + n − 1.
Separate instruction and data memories.