COA · Reading course
See how a computer
runs each instruction.
Every section from your supplied notes: instruction formats, addressing, datapaths, control, memory, pipelining, and I/O.
87 reading items · 9 phases · Worked examples & practice
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Lessons, chapter reviews, and checkpoints—in reading order.
Begin hereStart here0 / 2 complete
01Phase 0Foundations0 / 9 complete
0.1.1What a computer is: CPU, memory, I/O, buses; the stored-program idea; fetch–decode–executeLesson0.1.2Performance: clock, cycle time, CPI, execution time, MIPS, speedup, Amdahl's lawLessonLI-0.1The stored-program computerChapter review0.2.1Binary and hex, powers of two, size units, log₂: n bits name 2ⁿ thingsLesson0.2.2Signed integers: 2's complement, ranges, sign extension, overflow; bit fields and shiftsLesson0.2.3Digital building blocks: gates, MUX, decoder, adder, flip-flops, registers, clock, tri-state busLesson0.2.4Memory as an array: address, word, byte vs word addressing, endianness, alignmentLessonLI-0.2Bits & memory toolkitChapter reviewCP-0FoundationsCheckpoint
02Phase 1Instructions & Addressing Modes0 / 13 complete
1.1.1Instruction = opcode + operands; instruction formats; the instruction cycleLesson1.1.23-, 2-, 1- and 0-address machines: register, accumulator and stack codeLesson1.1.3Instruction types: data movement, ALU, shifts, compare and flags, branches and jumpsLesson1.1.4Instruction encoding: opcode space, register fields, expanding opcodesLessonLI-1.1Machine instructionsChapter review1.2.1Immediate, register, direct, indirect and register-indirect modesLesson1.2.2Displacement modes: indexed, base, PC-relative; auto-increment and auto-decrementLesson1.2.3Choosing modes: arrays, pointers, constants, relocatable code; memory references per modeLessonLI-1.2Addressing modesChapter review1.3.1Tracing programs: registers, memory and flags; counting memory references and cyclesLesson1.3.2Stack, subroutine call and return; RISC vs CISCLessonLI-1.3Programs on the machineChapter reviewCP-1Instructions & Addressing ModesCheckpoint
03Phase 2ALU & Datapath0 / 9 complete
2.1.1Building an ALU: 1-bit slice, n-bit ALU, subtraction, flags Z N C VLesson2.1.2Adder speed: ripple-carry delay, carry-lookahead (generate, propagate), gate-delay countingLesson2.1.3Multiplication: shift-and-add, Booth's algorithm; restoring divisionLessonLI-2.1ALU designChapter review2.2.1CPU registers and register transfer notation: PC, IR, MAR, MDR, GPRs, flags, SPLesson2.2.2Single-bus datapath: control signals and micro-operation steps for fetch and executeLesson2.2.3Two- and three-bus datapaths; counting cycles per instructionLessonLI-2.2DatapathChapter reviewCP-2ALU & DatapathCheckpoint
04Phase 3Control Unit0 / 8 complete
3.1.1Control signals, control steps and the step counter: what a control unit must produceLesson3.1.2Hardwired control: decoder, step counter and signal equationsLessonLI-3.1Hardwired controlChapter review3.2.1Microprogrammed control: control memory, control words, microroutines, µPCLesson3.2.2Microinstruction formats: horizontal vs vertical, field encoding, control-memory sizeLesson3.2.3Microprogram sequencing: next-address field, conditional branches; hardwired vs microprogrammedLessonLI-3.2Microprogrammed controlChapter reviewCP-3Control UnitCheckpoint
05Phase 4Memory Hierarchy & Cache0 / 18 complete
4.1.1Why a hierarchy: speed, cost, size; locality; hit, miss, hit ratioLesson4.1.2Average memory access time: hierarchical vs simultaneous access; multi-level formulasLesson4.1.3Memory chips: SRAM vs DRAM, ROM types, DRAM refresh; chip organisation 2ᵏ × nLesson4.1.4Memory interfacing: building larger memories from chips, address decoding, chip countsLesson4.1.5Secondary storage and bandwidth: disk access time, transfer rate, interleaved memoryLessonLI-4.1Hierarchy & main memoryChapter review4.2.1Cache lines and blocks; direct mapping: tag, line, offsetLesson4.2.2Fully associative and set-associative mapping; comparators and multiplexersLesson4.2.3Tag directory size and cache hardware: valid, dirty and replacement bitsLesson4.2.4Tracing references: hits and misses; compulsory, capacity and conflict missesLesson4.2.5Replacement policies: LRU, FIFO, random, optimal; tracing setsLessonLI-4.2Cache mappingChapter review4.3.1Write policies: write-through vs write-back, dirty bit, write-allocateLesson4.3.2Miss penalty and block transfer; memory-stall cycles; CPI with cache missesLesson4.3.3Multilevel caches: L1 and L2, local vs global miss rate, inclusionLesson4.3.4Programs and caches: array layout, loop order, counting missesLessonLI-4.3Cache performanceChapter reviewCP-4Memory Hierarchy & CacheCheckpoint
06Phase 5Pipelining0 / 13 complete
5.1.1The pipeline idea: stages, latches, cycle time, k + n − 1 cyclesLesson5.1.2Speedup, efficiency, throughput; unequal stages, latch delay, splitting stagesLesson5.1.3The 5-stage RISC pipeline IF ID EX MEM WB; space–time diagramsLessonLI-5.1Pipeline basicsChapter review5.2.1Structural hazards and stalls; CPI and speedup with stallsLesson5.2.2Data dependences: RAW, WAR, WAW; finding them in codeLesson5.2.3Handling data hazards: stalling, operand forwarding, the load-use hazardLesson5.2.4Control hazards: branch penalty, flushing, prediction, delayed branchLessonLI-5.2HazardsChapter review5.3.1Full cycle counting: mixed hazards and multi-cycle stagesLesson5.3.2Pipeline performance from an instruction mix: effective CPI, comparing designsLessonLI-5.3Putting it togetherChapter reviewCP-5PipeliningCheckpoint
07Phase 6I/O: Interrupts & DMA0 / 8 complete
6.1.1I/O devices, interfaces and ports; memory-mapped vs I/O-mapped I/O; busesLesson6.1.2Programmed I/O: polling, busy-waiting and its CPU costLessonLI-6.1I/O basicsChapter review6.2.1Interrupts: the interrupt cycle, ISR, context saving, vectored interrupts, priority and daisy chainLesson6.2.2Interrupt-driven I/O: overhead per transfer; interrupts vs pollingLesson6.2.3DMA: the controller, burst mode, cycle stealing, transparent mode; CPU time lostLessonLI-6.2Interrupts & DMAChapter reviewCP-6I/O: Interrupts & DMACheckpoint
08Phase 7Integration & Final Testrule sheet · 3 practice sets · drill · final test0 / 7 complete
7.1.17.1.1 — Master Rule Sheet (all rule cards merged)Revision7.2.17.2.1 — Mixed practice set 1Revision7.2.27.2.2 — Mixed practice set 2Revision7.2.37.2.3 — Mixed practice set 3Revision7.3.17.3.1 — GATE pattern drill: recurring patterns and fastest methodsRevision7.4.1Final end-to-end testFinal test7.4-keyFinal Test — Answer Key🛑Stop here until you have finished the 90-minute final test.🔑 Open the full answer keyQ1 Answer: (B)1 markSeparate instruction and data memories.(A) is wrong: One shared memory.(C) is wrong: Refers to operand style.(D) is wrong: Refers to operand style.Re-read: Lesson 0.1.1 — What a computer is: CPU, memory, I/O, buses; the stored-program idea; fetch–decode–executeQ2 Answer: 271 mark2⁷ × 2²⁰.Re-read: Lesson 0.2.1 — Binary and hex, powers of two, size units, log₂: n bits name 2ⁿ thingsQ3 Answer: (C)1 markBig-endian: 100 A1, 101 B2, 102 C3, 103 D4.(A) is wrong: Address 103.(B) is wrong: Address 100.(D) is wrong: Address 101.Re-read: Lesson 0.2.4 — Memory as an array: address, word, byte vs word addressing, endianness, alignmentQ4 Answer: 101 markOpcode 7, registers 15: 32 − 22.Re-read: Lesson 1.1.1 — Instruction = opcode + operands; instruction formats; the instruction cycleQ5 Answer: (B)1 markThe operand's address is itself in memory.(A) is wrong: That needs p in a register.(C) is wrong: For code-relative addresses.(D) is wrong: Not a constant.Re-read: Lesson 1.2.3 — Choosing modes: arrays, pointers, constants, relocatable code; memory references per modeQ6 Answer: 41 mark⌈log₂ 14⌉.Re-read: Lesson 2.1.1 — Building an ALU: 1-bit slice, n-bit ALU, subtraction, flags Z N C VQ7 Answer: (D)1 markMAR drives the address bus.(A) is wrong: Its value is copied into MAR.(B) is wrong: Holds the instruction.(C) is wrong: Holds data.Re-read: Lesson 2.2.1 — CPU registers and register transfer notation: PC, IR, MAR, MDR, GPRs, flags, SPQ8 Answer: (B)1 markA control-memory read per step; changes are microcode edits.(A) is wrong: That describes hardwired.(C) is wrong: Easier to modify.(D) is wrong: Not faster.Re-read: Lesson 3.2.3 — Microprogram sequencing: next-address field, conditional branches; hardwired vs microprogrammedQ9 Answer: 0.971 mark9700 / 10000.Re-read: Lesson 4.1.1 — Why a hierarchy: speed, cost, size; locality; hit, miss, hit ratioQ10 Answer: (B)1 markOne transistor and a capacitor per bit.(A) is wrong: SRAM is faster.(C) is wrong: Both are volatile.(D) is wrong: DRAM needs refresh.Re-read: Lesson 4.1.3 — Memory chips: SRAM vs DRAM, ROM types, DRAM refresh; chip organisation 2ᵏ × nQ11 Answer: 31 markOffset 5 bits, line 4 bits: (0x5A7C >> 5) mod 16 = 723 mod 16 = 3.Re-read: Lesson 4.2.1 — Cache lines and blocks; direct mapping: tag, line, offsetQ12 Answer: (B) (C) (D)1 markWrite-through writes memory on every hit.(A) is wrong: That is write-through.Re-read: Lesson 4.3.1 — Write policies: write-through vs write-back, dirty bit, write-allocateQ13 Answer: 1051 mark6 + 99.Re-read: Lesson 5.1.1 — The pipeline idea: stages, latches, cycle time, k + n − 1 cyclesQ14 Answer: (B) (D)1 markI2 reads R1 (RAW) and writes R1 (WAW).(A) is wrong: I1 does not read R1.(C) is wrong: I2 does not read R2.Re-read: Lesson 5.2.2 — Data dependences: RAW, WAR, WAW; finding them in codeQ15 Answer: (C)1 markOne bus cycle stolen per word.(A) is wrong: Transparent mode.(B) is wrong: Programmed I/O.(D) is wrong: Burst mode.Re-read: Lesson 6.2.3 — DMA: the controller, burst mode, cycle stealing, transparent mode; CPU time lostQ16 Answer: 32 marksCPI = 0.5 + 0.9 + 0.4 = 1.8; 2×10⁹ × 1.8 / 1.2×10⁹ = 3.Re-read: Lesson 0.1.2 — Performance: clock, cycle time, CPI, execution time, MIPS, speedup, Amdahl's lawQ17 Answer: 2242 marks65,536 − 49,152 − 12,800 = 3,584; ÷ 16 = 224.Re-read: Lesson 1.1.4 — Instruction encoding: opcode space, register fields, expanding opcodesQ18 Answer: 1232 marks2 + 30 × 4 + 1.Re-read: Lesson 1.3.1 — Tracing programs: registers, memory and flags; counting memory references and cyclesQ19 Answer: 52 marksAppend 0: 1001 1001 0. Pairs from the right: 10 (−1), 01 (+1), 00, 10 (−1), 11, 01 (+1), 00, 10 (−1). Recoded −1 0 +1 0 −1 0 +1 −1 = −128 + 32 − 8 + 2 − 1 = −103 ✓: 2 additions + 3 subtractions = 5.Re-read: Lesson 2.1.3 — Multiplication: shift-and-add, Booth's algorithm; restoring divisionQ20 Answer: 172 marks7 + 6 + 4.Re-read: Lesson 2.2.2 — Single-bus datapath: control signals and micro-operation steps for fetch and executeQ21 Answer: 262 marks3 + 4 + 4 + 2 = 13; + 3 + 10.Re-read: Lesson 3.2.3 — Microprogram sequencing: next-address field, conditional branches; hardwired vs microprogrammedQ22 Answer: 4.452 marks1 + 0.1 × (12 + 0.15 × 150) = 1 + 0.1 × 34.5.Re-read: Lesson 4.1.2 — Average memory access time: hierarchical vs simultaneous access; multi-level formulasQ23 Answer: 162 marks(1M/128K) × (8/4) = 8 × 2.Re-read: Lesson 4.1.4 — Memory interfacing: building larger memories from chips, address decoding, chip countsQ24 Answer: 819202 marksLines 4,096; sets 1,024 → 10; offset 6; tag 16; per line 20.Re-read: Lesson 4.2.3 — Tag directory size and cache hardware: valid, dirty and replacement bitsQ25 Answer: 42 marks2 sets; all odd → set 1 (4 ways): 1, 5, 9 M; 1 H; 5 H; 13 M; 1 H; 9 H.Re-read: Lesson 4.2.4 — Tracing references: hits and misses; compulsory, capacity and conflict missesQ26 Answer: 6.32 marksPenalty 80 ns = 160 cycles; 1.1 + 1.3 × 0.025 × 160 = 1.1 + 5.2.Re-read: Lesson 4.3.2 — Miss penalty and block transfer; memory-stall cycles; CPI with cache missesQ27 Answer: 102 marksOne load-use stall (ADD R5 after LOAD R4): 9 + 1.Re-read: Lesson 5.2.3 — Handling data hazards: stalling, operand forwarding, the load-use hazardQ28 Answer: 842 marksτ = 7; executed I1, I2, I3, I7, I8, I9: 12 cycles × 7.Re-read: Lesson 5.2.4 — Control hazards: branch penalty, flushing, prediction, delayed branchQ29 Answer: 163842 marksRows 512 B = 16 blocks apart; 512 lines → a column uses only 32 lines; blocks are evicted before reuse.Re-read: Lesson 4.3.4 — Programs and caches: array layout, loop order, counting missesQ30 Answer: 0.22 marksBlock time 4 ms; CPU 8 µs.Re-read: Lesson 6.2.3 — DMA: the controller, burst mode, cycle stealing, transparent mode; CPU time lostAnswer key
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