Twelve more mixed questions. Single-bus step counts use Lesson 2.2.2's tables.
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12 questions · 21 marks · 40 minutes. Negative marking on MCQ only: −1/3 mark for a wrong 1-mark MCQ, −2/3 for a wrong 2-mark MCQ. No negative marking for MSQ or NAT; MSQ has no partial credit.
Q1NAT1 markCPU time
A program executes 3 × 10⁹ instructions at CPI 1.2 on a 2.4 GHz processor. Time in seconds?
Numerical answer: ________
Q2NAT2 marksSingle-bus steps
Single bus (fetch 3 steps). Total control steps for ADD R1, R2, R3, then LOAD R4, (R5) (with one WMFC-only step), then a taken PC-relative branch?
Numerical answer: ________
Q3NAT2 marksChips
How many 64K × 4 chips make a 512 KB byte-addressable memory?
Numerical answer: ________
Q4NAT2 marksTag directory
Direct-mapped 64 KB cache, 32-byte blocks, 32-bit addresses, valid and dirty bits per line. Tag directory size in bits?
Numerical answer: ________
Q5NAT2 marksWrite-back
Write-back, hierarchical: t_c = 1 ns, block transfer 80 ns, h = 0.97, half of the evicted lines dirty. AMAT (ns)?
Numerical answer: ________
Q6NAT2 marksCPI with misses
Base CPI 1; I-cache miss rate 1%; D-cache miss rate 3%; 40% of instructions are loads/stores; miss penalty 150 cycles. Effective CPI?
Numerical answer: ________
Q7NAT2 marksBranch CPI
20% branches, 65% of them taken; predict-not-taken with a 3-cycle penalty. CPI?
Numerical answer: ________
Q8NAT2 marksLatency table
| S1 | S2 | S3 | S4 | |
|---|---|---|---|---|
| I1 | 1 | 2 | 1 | 1 |
| I2 | 1 | 1 | 2 | 1 |
| I3 | 2 | 1 | 1 | 1 |
Cycles to run I1, I2, I3 twice in a row?
Numerical answer: ________
Q9NAT1 markReturn address
A program starts at byte address 3000 with instructions of sizes 4, 4, 8, 4, 4 bytes. An interrupt arrives during the 4th instruction. Return address saved?
Numerical answer: ________
Q10NAT2 marksPolling
A 1 GHz CPU must poll a device delivering 3 MB/s (decimal) in 12-byte units, 200 cycles per poll. Percentage of CPU time?
Numerical answer: ________
Q11MCQ1 markDependence type
I1: ADD R1, R2, R3 and I2: SUB R2, R4, R5. The dependence from I1 to I2 is:
- (A) RAW
- (B) none
- (C) WAW
- (D) WAR
Q12NAT2 marksStack
SP = 0x2000 (8192), stack grows downward, 4-byte entries. After 5 pushes and 2 pops, what is SP in decimal?
Numerical answer: ________
✓Answer Vault
Answer Vault
Try the questions first. Open when you are ready to check.
Q1 Answer: 1.51 mark
3×10⁹ × 1.2 / 2.4×10⁹.
Re-read: Lesson 0.1.2 — Performance: clock, cycle time, CPI, execution time, MIPS, speedup, Amdahl's law
Q2 Answer: 172 marks
6 + 6 + 5.
Re-read: Lesson 2.2.2 — Single-bus datapath: control signals and micro-operation steps for fetch and execute
Q3 Answer: 162 marks
(512K / 64K) × (8 / 4) = 8 × 2.
Re-read: Lesson 4.1.4 — Memory interfacing: building larger memories from chips, address decoding, chip counts
Q4 Answer: 368642 marks
Lines 2,048 → 11 index bits; offset 5; tag 16; per line 18 → 36,864.
Re-read: Lesson 4.2.3 — Tag directory size and cache hardware: valid, dirty and replacement bits
Q5 Answer: 4.62 marks
1 + 0.03 × (80 + 40) = 4.6.
Re-read: Lesson 4.3.1 — Write policies: write-through vs write-back, dirty bit, write-allocate
Q6 Answer: 4.32 marks
1 + 1.5 + 0.4 × 0.03 × 150 = 1 + 1.5 + 1.8.
Re-read: Lesson 4.3.2 — Miss penalty and block transfer; memory-stall cycles; CPI with cache misses
Q7 Answer: 1.392 marks
1 + 0.2 × 0.65 × 3.
Re-read: Lesson 5.2.4 — Control hazards: branch penalty, flushing, prediction, delayed branch
Q8 Answer: 122 marks
Apply the cell rule to all six instructions; the last S4 ends in cycle 12.
Re-read: Lesson 5.3.1 — Full cycle counting: mixed hazards and multi-cycle stages
Q9 Answer: 30201 mark
Starts: 3000, 3004, 3008, 3016, 3020. The 4th (3016) completes; next is 3020.
Re-read: Lesson 6.2.1 — Interrupts: the interrupt cycle, ISR, context saving, vectored interrupts, priority and daisy chain
Q10 Answer: 52 marks
250,000 polls × 200 = 5×10⁷.
Re-read: Lesson 6.1.2 — Programmed I/O: polling, busy-waiting and its CPU cost
Q11 Answer: (D)1 mark
I2 writes R2, which I1 reads.
- (A) is wrong: I2 does not read R1.
- (B) is wrong: There is a name dependence on R2.
- (C) is wrong: They write different registers.
Re-read: Lesson 5.2.2 — Data dependences: RAW, WAR, WAW; finding them in code
Q12 Answer: 81802 marks
8192 − 4 × 3.
Re-read: Lesson 1.3.2 — Stack, subroutine call and return; RISC vs CISC