Hazards

ACompressed recap

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Hazards: structural (hardware), data (RAW true; WAR/WAW name dependences, only with out-of-order completion), control (branches). CPI = 1 + stalls; speedup = k/(1 + stalls); cycles = k + n − 1 + stalls. Without forwarding (split RF): 2/1/0 stalls for distance 1/2/3; with forwarding: ALU→ALU 0, load-use 1. Branch penalty = r − 1; stall CPI = 1 + f_b·penalty; predict-not-taken 1 + f_b·p_taken·penalty; delay slots always execute.

BMerged rule card

5.2.1 Structural hazards and stalls; CPI and speedup with stalls

• Hazards: structural (hardware), data (values), control (branches).
• Stall = bubble; CPI = 1 + average stalls.
• Speedup (balanced, no overhead) = k / (1 + stalls); in general (CPI·T)_np / (CPI·T)_p.
• Total cycles = k + n − 1 + stalls.

5.2.2 Data dependences: RAW, WAR, WAW; finding them in code

• RAW: later reads what earlier writes (true). WAR: later writes what earlier reads (anti). WAW: both write (output).
• Count only nearest pairs (no intervening write).
• In-order 5-stage: only RAW stalls. Renaming removes WAR/WAW.

5.2.3 Handling data hazards: stalling, operand forwarding, the load-use hazard

• No forwarding, split RF: stalls 2/1/0 for distance 1/2/3 (no split: 3/2/1).
• Forwarding: ALU→ALU 0 stalls; load→next use 1 stall; distance 2 after a load: 0.
• Cycles = k + n − 1 + stalls; draw the diagram when dependences overlap.
• Scheduling independent instructions after loads hides the load-use stall.

5.2.4 Control hazards: branch penalty, flushing, prediction, delayed branch

• Penalty = r − 1 (resolution at the end of stage r): EX → 2, ID → 1.
• Stall: CPI = 1 + f_b·penalty. Predict-not-taken: 1 + f_b·p_taken·penalty.
• Delay slots always execute; filled slots hide penalty.
• Count only executed instructions; next fetch after resolution.

CInterleaved GATE-style questions

Q1NAT2 marksSpeedup

Balanced 5-stage pipeline; 30% of instructions incur 1 stall, 5% incur 4 stalls. Speedup over non-pipelined?

Numerical answer: ________

Q2NAT2 marksDependences

Count all dependences (RAW + WAR + WAW): I1: ADD R1, R2, R3 · I2: SUB R2, R1, R4 · I3: MUL R1, R2, R2.

Numerical answer: ________

Q3NAT2 marksForwarding

With forwarding: LOAD R1, 0(R2) · LOAD R3, 4(R2) · ADD R4, R1, R3 · STORE R4, 8(R2). Cycles?

Numerical answer: ________

Q4NAT2 marksNo forwarding

The same four instructions without forwarding (split RF). Cycles?

Numerical answer: ________

Q5NAT1 markBranch penalty

Branches are resolved at the end of ID in a 5-stage pipeline that stalls on branches. Penalty?

Numerical answer: ________

Q6NAT2 marksBranch CPI

15% branches, all stalled for 3 cycles; plus 20% loads, half of them followed by a dependent instruction (1 stall). CPI?

Numerical answer: ________

Q7MCQ1 markLoad-use

Which situation still needs a stall even with full forwarding?

• (A) An ALU result used two instructions later
• (B) A loaded value used by a store's data two instructions later
• (C) An ALU result used by the next instruction
• (D) A loaded value used by the next instruction

Q8MSQ2 marksHazard kinds

Which pairs are matched correctly?

• (A) Single memory port — structural hazard
• (B) WAW — structural hazard
• (C) RAW — data hazard
• (D) Branch — control hazard

DAnswer Vault