Two- and three-bus datapaths; counting cycles per instruction

0 · Recall Warm-up

Answer from memory first. Answers are in the Answer Vault at the bottom.

• Single bus: execute steps for a register–register ADD? from Lesson 2.2.2
• Which register holds data read from memory? from Lesson 2.2.1
• 16-bit CLA blocks rippled, how many gate delays per block after g/p? from Lesson 2.1.2

1 · The Hook

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The single bus is cheap but slow: three steps just to add two registers. Add more buses and the ALU can get both operands and return its result in the same step. GATE questions describe a datapath in a sentence or two and ask for the minimum number of cycles; the skill is to see which transfers can share a step.

2 · Predict First

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A datapath has three buses: A and B carry two register values to the ALU, and C carries the ALU's result back to a register, all in one step. How many steps does the execute phase of ADD R1, R2, R3 need?

Make a guess in your head. The answer opens Section 3.

3 · Core Concept

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Predict First — the answer

One: R2 on bus A, R3 on bus B, ALU adds, result on bus C into R1, all in the same step.

Three-bus organisation

• Register file with two read ports (onto buses A and B) and one write port (from bus C).
• ALU inputs from A and B; ALU output on C.
• PC has its own incrementer (no ALU needed for PC + 4).

Fetch (3 steps, the middle one waiting for memory):

Execute ADD R1, R2, R3: 1 step (R2 on A, R3 on B, Add, R1 ← C, End).

Two-bus organisation (one common model)

• Two source buses carry two values into the ALU in one step, but the result must be latched (in Z) and returned over a bus in the next step.
• Execute ADD R1, R2, R3: step 1: R2, R3 → ALU → Z; step 2: Z → R1. 2 steps.

Comparison (execute phase, R1 ← R2 + R3)

How to count steps for any described datapath

• Write the instruction as register transfers (RTL).
• For each step, a bus carries one value; the ALU does one operation; a register is written at the end of the step; a value written in a step is readable only in the next.
• Memory: a step to place the address (and Read), the data available after MFC (count the wait as a step if the question says memory takes a cycle).
• Pack transfers into the fewest steps without breaking these rules.

A GATE-style example

"All registers and the ALU are on one bus; the ALU has temporary input register S and output register T; a memory read takes two cycles (load MAR, then data into MDR)." Execute ADD R0, R1 (R0 ← R0 + R1): S ← R0; T ← S + R1; R0 ← T: 3 cycles, the single-bus pattern with Y = S and Z = T.

4 · Visual

Single bus                 Two buses                  Three buses
step 1: Y <- R2            step 1: Z <- R2 + R3       step 1: R1 <- R2 + R3
step 2: Z <- Y + R3        step 2: R1 <- Z
step 3: R1 <- Z

        bus                    bus A   bus B             bus A   bus B   bus C
         |                       |       |                 |       |       ^
  R2 -> Y -> ALU <- R3     R2 -> ALU <- R3 -> Z      R2 -> ALU <- R3 ----+-> R1

5 · Worked Examples

Example 1 Easy

On the three-bus datapath, how many total steps (fetch included) for SUB R4, R5, R6?

Solution

Fetch 3 + execute 1 = 4.

Example 2 Medium

A program executes 1,000 register–register ALU instructions. How many control steps are saved by a three-bus datapath over a single bus? Fetch: 3 steps in both.

Solution

Execute steps: 3 vs 1 → 2 saved per instruction: 2,000 steps.

Example 3 GATE

Single-bus CPU as in Lesson 2.2.2. A two-word instruction ADDI R1, #imm keeps the immediate in the second word, at the address after the first word. How many steps does the execute phase need to fetch the immediate and add it? (Use: MAR ← PC; Read; PC ← PC + 4 via the ALU as in the fetch; then add.)

Solution

4: PCout, MARin, Read, Select4, Add, Zin · 5: Zout, PCin, WMFC · 6: R1out, Yin · 7: MDRout, SelectY, Add, Zin · 8: Zout, R1in, End. 5 steps. R1out cannot join step 5, because Zout already uses the bus there.

6 · GATE Traps

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• More buses cut execute steps; the memory wait in the fetch does not disappear.
• In the two-bus model, the result still needs a second step to reach the register.
• A value written at the end of a step is available only from the next step.
• Read the question's datapath description: it overrides any textbook model.

7 · Memory Hook

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"Three buses, one step; two buses, two; one bus, three." (For R1 ← R2 + R3.)

8 · Connect the Dots

Phase 2 is complete: the ALU inside, and the datapath that moves values. Who raises PCout, MARin and Add at exactly the right step? The control unit, Phase 3: first built from logic gates (hardwired), then from a memory of control words (microprogrammed).

9 · Self-Test

GATE format. Try every question before opening the vault.

Q1NAT1 markThree-bus execute

On the three-bus datapath, how many steps does the execute phase of ADD R1, R2, R3 take?

Numerical answer: ________

Q2NAT2 marksSteps saved

A program runs 5,000 register–register ALU instructions. A single-bus CPU needs 3 execute steps for each; a two-bus CPU needs 2. Fetch costs the same. How many steps does the two-bus CPU save?

Numerical answer: ________

Q3MCQ1 markTwo-bus

In the two-bus model of the lesson, why does ADD R1, R2, R3 need 2 steps?

• (A) The PC must be incremented first
• (B) Memory must be read twice
• (C) The result must be latched and sent to R1 in the next step
• (D) The ALU is slower

Q4NAT2 marksTotal steps

A single-bus CPU runs 100 instructions: 60 register–register ALU instructions (3 + 3 steps each) and 40 ADD R, (R) instructions (3 + 4 steps each). Total control steps?

Numerical answer: ________

Q5MSQ2 marksDatapath rules

Which statements are true?

• (A) With an incrementer, the PC update does not need the ALU.
• (B) A three-bus datapath needs a register file with two read ports and one write port.
• (C) A value written into a register in a step can be read only in a later step.
• (D) Adding buses removes the need to wait for memory.

10 · Rule Card

• Three-bus: R1 ← R2 + R3 in 1 step; two-bus: 2 steps; single bus: 3 steps.
• Counting: one value per bus per step; one ALU op per step; written values readable next step.
• Memory reads need an address step and a data step (or WMFC).
• The question's datapath description always wins.

11 · Concept Ledger

Unlocked in this lesson. From here on, these terms may be used.

two-bus organisationthree-bus organisationregister-file read/write portsPC incrementerstep-counting methoddatapath comparison

12 · Answer Vault