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These notes take you from zero to full marks in GATE Computer Organization & Architecture. Read in order: every lesson uses only ideas taught before it. Each lesson takes 20–35 minutes.
Every lesson has the same sections. Questions always come before answers. Answers sit in a closed Answer Vault at the bottom of each lesson; the Predict First answer opens Section 3.
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Spaced recall. Each lesson opens with 3 warm-up questions: one from the previous lesson, one from about 3 lessons back, one from 7 or more lessons back.
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Verified. Computable answers were re-computed by code before they were written down: address splits and tag sizes, cache hit/miss traces, pipeline cycle counts (with a pipeline simulator), opcode encodings, Booth recoding, chip counts, access times and I/O overheads.
Your commands, on this page
| Command | Here |
|---|---|
| next | The “Type next →” link at the end of every lesson. |
| roadmap | The roadmap below and the sidebar. Press Mark as done on a lesson and it gets a ✅ in both (stored in this browser). |
| revise [lesson ID] | Search the sidebar for the ID, or use that lesson's Rule Card and the Master Rule Sheet (7.1.1). |
| simpler / deeper | Ask Claude in chat, naming the lesson ID. Deeper practice for every chapter is in its Lock-in and in Phase 7. |
| start final test | Lesson 7.4.1. The test page shows no answers. |
| submit | Enter your answers in 7.4.1 and press Submit answers: score with GATE negative marking, topic-wise accuracy, the questions you got wrong and the lessons to re-read. |
| key | The very last section of the notes. |
Conventions used throughout
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- One running example. Many lessons reuse the same small program, the array-sum loop
sum = sum + A[i]for i = 0 … n−1. You will write it in machine code (Phase 1), run it through the datapath (Phase 2), watch it hit the cache (Phase 4) and flow down the pipeline (Phase 5). - Memory sizes are binary: 1 K = 2¹⁰, 1 M = 2²⁰, 1 G = 2³⁰. Times and rates are decimal: 1 MHz = 10⁶ Hz, 1 ns = 10⁻⁹ s. If a GATE question says otherwise, the question wins.
- B = byte, b = bit. Memory is byte-addressable unless a question says word-addressable.
- Pipeline cycles are numbered from 1: the first instruction is fetched in cycle 1. Unless stated, the register file is written in the first half of a cycle and read in the second half (Lesson 5.1.3).
- Marks follow GATE: MCQ wrong answers cost 1/3 (1-mark) or 2/3 (2-mark); MSQ and NAT have no negative marking; MSQ has no partial credit.
- Number representation and IEEE 754 floating point belong to the Digital Logic section of the syllabus; Lesson 0.2.2 recaps only the integer part COA needs.