3.1.2 Hardwired control: decoder, step counter and signal equations

0 · Recall Warm-up

Answer from memory first. Answers are in the Answer Vault at the bottom.

Step-counter bits for 11 steps? from Lesson 3.1.1
Single bus: execute steps of ADD R1, (R3)? from Lesson 2.2.2
Additions in Booth's algorithm for 0111? from Lesson 2.1.3

1 · The Hook

🎣

A hardwired control unit is a big piece of combinational logic: each control signal gets its own equation, an OR of "this instruction AND this step". It is the fastest way to generate signals, and RISC processors use it. GATE asks you to read or write those equations.

2 · Predict First

🤔

Using Lesson 2.2.2's step tables, in which steps is Zin = 1 for the three instructions ADD (register), ADD (memory operand) and BR (branch)? Write Zin as a logic expression.

Make a guess in your head. The answer opens Section 3.

3 · Core Concept

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Predict First — the answer

Fetch step T1 (all instructions); ADD register: T5; ADD memory: T6; BR: T4. So Zin = T1 + T5·ADDreg + T6·ADDmem + T4·BR.

Structure

Instruction decoder: opcode (k bits) → one line per instruction: INS₁ … INS_m (a k-to-2ᵏ decoder).
Step decoder: step counter → T1 … Tn.
Encoder (logic network): AND/OR gates combine INSᵢ, Tⱼ and flags into each control signal.

Writing a signal's equation

Look up every (instruction, step) where the signal is 1 in the step tables, AND each pair, OR them all. From Lesson 2.2.2 (ADDreg = ADD R1, R2, R3, ADDmem = ADD R1, (R3), BR = unconditional branch):

Zin = T1 + T5·ADDreg + T6·ADDmem + T4·BR
Yin = T2 + T4·ADDreg + T5·ADDmem
End = T6·ADDreg + T7·ADDmem + T5·BR
MARin = T1 + T4·ADDmem

A conditional branch BRN ("branch if N = 1") adds flags: in step 4 it continues only if N = 1, otherwise ends: End = … + T4·BRN·N̄ + T5·BRN·N.

WMFC behaviour: the counter's enable is NOT(WMFC) + MFC: it advances unless the current step waits and memory has not finished.

Pros and cons

Hardwired
Speed	fastest: signals come out of gates, no memory to read
Flexibility	poor: changing an instruction means redesigning logic
Complexity	grows quickly with many complex instructions and modes
Used in	RISC processors (few simple instructions)

Sizes to know

Opcode decoder: k inputs, 2ᵏ outputs.
Step decoder: ⌈log₂ n⌉-bit counter, n outputs.
Each signal's equation has one AND term per (instruction, step) where it is active.

4 · Visual

Diagram: INS1…INSm · T1…Tn · IR opcode · Instruction decoder · Step counter · Step decoder · AND–OR encoder · signals · flags, MFC

Hardwired control: decoders feed a fixed logic network, one output per control signal.

5 · Worked Examples

Example 1 Easy

Write the equation for IRin using the single-bus fetch.

Solution

IRin is active only in fetch step 3, for every instruction: IRin = T3.

Example 2 Medium

Write R1in for the three instructions ADDreg, ADDmem, BR (R1 is the destination of both adds).

Solution

ADDreg step 6, ADDmem step 7: R1in = T6·ADDreg + T7·ADDmem.

Example 3 GATE

A CPU has a 6-bit opcode and instructions of at most 12 steps. What decoders does a hardwired control unit need?

Solution

A 6-to-64 instruction decoder and a 4-bit step counter with a 4-to-16 step decoder (only T1…T12 used).

6 · GATE Traps

⚠️

Fetch-step terms (T1, T2, T3) have no instruction factor: they hold for every instruction.
Conditional signals include the flag (or its complement) in the AND term.
Hardwired is faster but less flexible than microprogrammed.
The step decoder needs ⌈log₂ n⌉ input bits for n steps.

7 · Memory Hook

🧠

"Signal = OR of (instruction AND step)." Read the step table column by column.

8 · Connect the Dots

Chapter 3.1 is complete: what the control unit must produce, and the hardwired way to produce it. Chapter 3.2 stores the step tables in memory instead: microprogrammed control.

9 · Self-Test

GATE format. Try every question before opening the vault.

Q1MCQ1 markEquation

Using the lesson's three instructions, which is the correct equation for Yin?

(A) Yin = T2 + T4·ADDreg + T5·ADDmem
(B) Yin = T1 + T4·ADDreg
(C) Yin = T2·BR + T5·ADDmem
(D) Yin = T4 + T5

Q2NAT1 markDecoder outputs

A hardwired control unit uses a full decoder on a 7-bit opcode. How many output lines?

Numerical answer: ________

Q3MSQ2 marksHardwired properties

Which are true of hardwired control?

(A) It is usually faster than microprogrammed control.
(B) Adding a new instruction is easy: just add a word to a memory.
(C) Each control signal is a logic function of instruction, step and flags.
(D) It is typical of RISC processors.

Q4NAT2 marksAND terms

Signal X is active in fetch step T1 for all instructions, and additionally in step T4 of 5 instructions and step T6 of 3 instructions. How many AND terms (product terms), counting T1 as one term, are in X's sum-of-products equation?

Numerical answer: ________

Q5MCQ1 markConditional end

For "branch if Z = 1" (BZ), which decides in step 4 whether the instruction ends?

(A) T4·BZ·Z̄ in the End equation
(B) T4 alone
(C) T4·BZ·Z in the End equation
(D) BZ alone

10 · Rule Card

Hardwired = instruction decoder + step decoder + AND–OR network (+ flags).
Signal = Σ (Tⱼ · INSᵢ [· flag]); fetch steps carry no instruction factor.
Counter enable = NOT(WMFC) + MFC.
Fast, inflexible, RISC-style.

11 · Concept Ledger

Unlocked in this lesson. From here on, these terms may be used.

instruction decoderstep decoderAND–OR encoder networkcontrol-signal equationconditional End termcounter enablehardwired control pros and cons

12 · Answer Vault

Answer Vault

Try the questions first. Open when you are ready to check.

Recall Warm-up

4 (R3out, MARin, Read · R1out, Yin, WMFC · MDRout, SelectY, Add, Zin · Zout, R1in, End).
1 (and 1 subtraction).