Lesson IDs are Phase.Chapter.Topic, for example 4.2.1 is Phase 4, Chapter 4.2, Topic 1. The order is a prerequisite chain. ✅ marks what you have marked as done.

🧭 PHASE 0 — FOUNDATIONS

• Ch 0.1 The stored-program computer
• 0.1.1 What a computer is: CPU, memory, I/O, buses; the stored-program idea; fetch–decode–execute
• 0.1.2 Performance: clock, cycle time, CPI, execution time, MIPS, speedup, Amdahl's law
• LI-0.1 Chapter 0.1 Lock-in Lock-in
• Ch 0.2 Bits & memory toolkit
• 0.2.1 Binary and hex, powers of two, size units, log₂: n bits name 2ⁿ things
• 0.2.2 Signed integers: 2's complement, ranges, sign extension, overflow; bit fields and shifts
• 0.2.3 Digital building blocks: gates, MUX, decoder, adder, flip-flops, registers, clock, tri-state bus
• 0.2.4 Memory as an array: address, word, byte vs word addressing, endianness, alignment
• LI-0.2 Chapter 0.2 Lock-in Lock-in
• CP-0 Phase 0 Checkpoint (15 questions) Checkpoint

🧾 PHASE 1 — INSTRUCTIONS & ADDRESSING MODES

• Ch 1.1 Machine instructions
• 1.1.1 Instruction = opcode + operands; instruction formats; the instruction cycle
• 1.1.2 3-, 2-, 1- and 0-address machines: register, accumulator and stack code
• 1.1.3 Instruction types: data movement, ALU, shifts, compare and flags, branches and jumps
• 1.1.4 Instruction encoding: opcode space, register fields, expanding opcodes GATE favourite
• LI-1.1 Chapter 1.1 Lock-in Lock-in
• Ch 1.2 Addressing modes
• 1.2.1 Immediate, register, direct, indirect and register-indirect modes GATE favourite
• 1.2.2 Displacement modes: indexed, base, PC-relative; auto-increment and auto-decrement GATE favourite
• 1.2.3 Choosing modes: arrays, pointers, constants, relocatable code; memory references per mode GATE favourite
• LI-1.2 Chapter 1.2 Lock-in Lock-in
• Ch 1.3 Programs on the machine
• 1.3.1 Tracing programs: registers, memory and flags; counting memory references and cycles GATE favourite
• 1.3.2 Stack, subroutine call and return; RISC vs CISC
• LI-1.3 Chapter 1.3 Lock-in Lock-in
• CP-1 Phase 1 Checkpoint (15 questions) Checkpoint

⚙️ PHASE 2 — ALU & DATAPATH

• Ch 2.1 ALU design
• 2.1.1 Building an ALU: 1-bit slice, n-bit ALU, subtraction, flags Z N C V
• 2.1.2 Adder speed: ripple-carry delay, carry-lookahead (generate, propagate), gate-delay counting
• 2.1.3 Multiplication: shift-and-add, Booth's algorithm; restoring division
• LI-2.1 Chapter 2.1 Lock-in Lock-in
• Ch 2.2 Datapath
• 2.2.1 CPU registers and register transfer notation: PC, IR, MAR, MDR, GPRs, flags, SP
• 2.2.2 Single-bus datapath: control signals and micro-operation steps for fetch and execute GATE favourite
• 2.2.3 Two- and three-bus datapaths; counting cycles per instruction
• LI-2.2 Chapter 2.2 Lock-in Lock-in
• CP-2 Phase 2 Checkpoint (15 questions) Checkpoint

🎛️ PHASE 3 — CONTROL UNIT

• Ch 3.1 Hardwired control
• 3.1.1 Control signals, control steps and the step counter: what a control unit must produce
• 3.1.2 Hardwired control: decoder, step counter and signal equations
• LI-3.1 Chapter 3.1 Lock-in Lock-in
• Ch 3.2 Microprogrammed control
• 3.2.1 Microprogrammed control: control memory, control words, microroutines, µPC
• 3.2.2 Microinstruction formats: horizontal vs vertical, field encoding, control-memory size GATE favourite
• 3.2.3 Microprogram sequencing: next-address field, conditional branches; hardwired vs microprogrammed
• LI-3.2 Chapter 3.2 Lock-in Lock-in
• CP-3 Phase 3 Checkpoint (15 questions) Checkpoint

🗃️ PHASE 4 — MEMORY HIERARCHY & CACHE

• Ch 4.1 Hierarchy & main memory
• 4.1.1 Why a hierarchy: speed, cost, size; locality; hit, miss, hit ratio GATE favourite
• 4.1.2 Average memory access time: hierarchical vs simultaneous access; multi-level formulas GATE favourite
• 4.1.3 Memory chips: SRAM vs DRAM, ROM types, DRAM refresh; chip organisation 2ᵏ × n
• 4.1.4 Memory interfacing: building larger memories from chips, address decoding, chip counts
• 4.1.5 Secondary storage and bandwidth: disk access time, transfer rate, interleaved memory
• LI-4.1 Chapter 4.1 Lock-in Lock-in
• Ch 4.2 Cache mapping
• 4.2.1 Cache lines and blocks; direct mapping: tag, line, offset GATE favourite
• 4.2.2 Fully associative and set-associative mapping; comparators and multiplexers GATE favourite
• 4.2.3 Tag directory size and cache hardware: valid, dirty and replacement bits GATE favourite
• 4.2.4 Tracing references: hits and misses; compulsory, capacity and conflict misses GATE favourite
• 4.2.5 Replacement policies: LRU, FIFO, random, optimal; tracing sets GATE favourite
• LI-4.2 Chapter 4.2 Lock-in Lock-in
• Ch 4.3 Cache performance
• 4.3.1 Write policies: write-through vs write-back, dirty bit, write-allocate GATE favourite
• 4.3.2 Miss penalty and block transfer; memory-stall cycles; CPI with cache misses GATE favourite
• 4.3.3 Multilevel caches: L1 and L2, local vs global miss rate, inclusion
• 4.3.4 Programs and caches: array layout, loop order, counting misses GATE favourite
• LI-4.3 Chapter 4.3 Lock-in Lock-in
• CP-4 Phase 4 Checkpoint (15 questions) Checkpoint

🏭 PHASE 5 — PIPELINING

• Ch 5.1 Pipeline basics
• 5.1.1 The pipeline idea: stages, latches, cycle time, k + n − 1 cycles GATE favourite
• 5.1.2 Speedup, efficiency, throughput; unequal stages, latch delay, splitting stages GATE favourite
• 5.1.3 The 5-stage RISC pipeline IF ID EX MEM WB; space–time diagrams
• LI-5.1 Chapter 5.1 Lock-in Lock-in
• Ch 5.2 Hazards
• 5.2.1 Structural hazards and stalls; CPI and speedup with stalls GATE favourite
• 5.2.2 Data dependences: RAW, WAR, WAW; finding them in code GATE favourite
• 5.2.3 Handling data hazards: stalling, operand forwarding, the load-use hazard GATE favourite
• 5.2.4 Control hazards: branch penalty, flushing, prediction, delayed branch GATE favourite
• LI-5.2 Chapter 5.2 Lock-in Lock-in
• Ch 5.3 Putting it together
• 5.3.1 Full cycle counting: mixed hazards and multi-cycle stages GATE favourite
• 5.3.2 Pipeline performance from an instruction mix: effective CPI, comparing designs GATE favourite
• LI-5.3 Chapter 5.3 Lock-in Lock-in
• CP-5 Phase 5 Checkpoint (15 questions) Checkpoint

🔌 PHASE 6 — I/O: INTERRUPTS & DMA

• Ch 6.1 I/O basics
• 6.1.1 I/O devices, interfaces and ports; memory-mapped vs I/O-mapped I/O; buses
• 6.1.2 Programmed I/O: polling, busy-waiting and its CPU cost
• LI-6.1 Chapter 6.1 Lock-in Lock-in
• Ch 6.2 Interrupts & DMA
• 6.2.1 Interrupts: the interrupt cycle, ISR, context saving, vectored interrupts, priority and daisy chain GATE favourite
• 6.2.2 Interrupt-driven I/O: overhead per transfer; interrupts vs polling
• 6.2.3 DMA: the controller, burst mode, cycle stealing, transparent mode; CPU time lost GATE favourite
• LI-6.2 Chapter 6.2 Lock-in Lock-in
• CP-6 Phase 6 Checkpoint (15 questions) Checkpoint

🏁 PHASE 7 — INTEGRATION & FINAL TEST

• Ch 7.1 Master rule sheet
• 7.1.1 Master Rule Sheet (all rule cards merged) Revision
• Ch 7.2 Mixed practice
• 7.2.1 Mixed practice set 1 Revision
• 7.2.2 Mixed practice set 2 Revision
• 7.2.3 Mixed practice set 3 Revision
• Ch 7.3 GATE pattern drill
• 7.3.1 GATE pattern drill: recurring patterns and fastest methods Revision
• Ch 7.4 Final test
• 7.4.1 Final end-to-end test (30 questions, 90 min) Final test

Phases

🧭

Phase 0 · Foundations

6 lessons · 2 lock-ins · checkpoint

🧾

Phase 1 · Instructions & Addressing Modes

9 lessons · 3 lock-ins · checkpoint

⚙️

Phase 2 · ALU & Datapath

6 lessons · 2 lock-ins · checkpoint

🎛️

Phase 3 · Control Unit

5 lessons · 2 lock-ins · checkpoint

🗃️

Phase 4 · Memory Hierarchy & Cache

14 lessons · 3 lock-ins · checkpoint

🏭

Phase 5 · Pipelining

9 lessons · 3 lock-ins · checkpoint

🔌

Phase 6 · I/O: Interrupts & DMA

5 lessons · 2 lock-ins · checkpoint

🏁

Phase 7 · Integration & Final Test

rule sheet · 3 practice sets · drill · final test

🧭Phase 0 — Foundations