ACompressed recap
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Latch: cross-coupled gates; NOR SR (S = R = 1 forbidden), NAND S̄R̄ (00 forbidden), gated D latch transparent while enabled. Flip-flops (edge-triggered): D Q⁺ = D, T Q⁺ = T ⊕ Q, JK Q⁺ = JQ' + K'Q, SR Q⁺ = S + R'Q. Excitation: JK 0x/1x/x1/x0; T = Q ⊕ Q⁺. Race-around in level JK. Conversions via excitation tables. f_max = 1/(t_pd + t_comb + t_su).
BMerged rule card
6.1.1 Latches: the SR latch and the gated D latch
- Latch = cross-coupled gates with feedback; stores one bit; level-sensitive.
- NOR SR latch: S = 1 sets, R = 1 resets, 00 holds, 11 forbidden.
- NAND S̄R̄ latch: 0 sets/resets (active-low), 11 holds, 00 forbidden.
- Gated D latch: E = 1 → Q = D (transparent); E = 0 → hold.
6.1.2 Flip-flops: SR, D, JK and T; characteristic and excitation tables
- Edge-triggered: inputs sampled only at the clock edge.
- D: Q⁺ = D. T: Q⁺ = T ⊕ Q. JK: Q⁺ = JQ' + K'Q (11 toggles). SR: Q⁺ = S + R'Q, SR = 0.
- Excitation (Q → Q⁺): D = Q⁺; T = Q ⊕ Q⁺; JK: 0→0 0x, 0→1 1x, 1→0 x1, 1→1 x0; SR: 0x, 10, 01, x0.
- Race-around in level-triggered JK with J = K = 1; fixed by master–slave or edge triggering.
6.1.3 Converting flip-flops; timing and the maximum clock frequency
- Conversion: X's characteristic table → Y's excitation → minimise. D from JK: J = D, K = D'; T from JK: J = K = T; T from D: D = T ⊕ Q; JK from D: D = JQ' + K'Q.
- Setup before the edge, hold after, t_pd from edge to output.
- T_min = t_pd + t_comb(max) + t_su (+ skew); f_max = 1/T_min. Hold: t_pd + t_comb(min) ≥ t_h.
CInterleaved GATE-style questions
Q1MCQ1 markLatch
A NAND S̄R̄ latch has S̄ = 0, R̄ = 0. This is:
- (A) hold
- (B) forbidden
- (C) set
- (D) reset
Q2MCQ1 markTransparency
Which device is transparent while its enable/clock is high?
- (A) Gated D latch
- (B) Positive-edge D flip-flop
- (C) Master–slave JK flip-flop
- (D) T flip-flop
Q3NAT1 markSR
An SR flip-flop has Q = 0, S = 1, R = 0. What is Q⁺?
Numerical answer: ________
Q4NAT2 marksJK trace
A JK flip-flop starts at Q = 0. Edges with (J, K) = (1, 0), (0, 0), (1, 1), (1, 1), (0, 1), (1, 1). After the last edge, Q = ?
Numerical answer: ________
Q5MCQ1 markExcitation
For an SR flip-flop, the transition 1 → 0 requires:
- (A) S = x, R = 0
- (B) S = 0, R = 1
- (C) S = 0, R = x
- (D) S = 1, R = 0
Q6MCQ1 markConversion
A JK flip-flop with J = K = T behaves like:
- (A) a D flip-flop
- (B) a buffer
- (C) an SR latch
- (D) a T flip-flop
Q7NAT2 marksFrequency
t_pd = 6 ns, logic 15 ns, setup 4 ns. Maximum clock frequency (MHz)?
Numerical answer: ________
Q8NAT1 markPeriod
A flip-flop drives another directly (no logic). t_pd = 3 ns, setup 2 ns. Minimum clock period (ns)?
Numerical answer: ________
DAnswer Vault
Answer Vault
Try the questions first. Open when you are ready to check.
Q1 Answer: (B)1 mark
Both outputs go to 1.
- (A) is wrong: 11 holds.
- (C) is wrong: 01 sets.
- (D) is wrong: 10 resets.
Re-read: Lesson 6.1.1 — Latches: the SR latch and the gated D latch
Q2 Answer: (A)1 mark
It passes D straight through.
- (B) is wrong: Edge-triggered.
- (C) is wrong: Not transparent.
- (D) is wrong: Edge-triggered.
Re-read: Lesson 6.1.1 — Latches: the SR latch and the gated D latch
Q3 Answer: 11 mark
Set.
Re-read: Lesson 6.1.2 — Flip-flops: SR, D, JK and T; characteristic and excitation tables
Q4 Answer: 12 marks
1, 1, 0, 1, 0, 1.
Re-read: Lesson 6.1.2 — Flip-flops: SR, D, JK and T; characteristic and excitation tables
Q5 Answer: (B)1 mark
Reset.
- (A) is wrong: That is 1 → 1.
- (C) is wrong: That is 0 → 0.
- (D) is wrong: Set.
Re-read: Lesson 6.1.2 — Flip-flops: SR, D, JK and T; characteristic and excitation tables
Q6 Answer: (D)1 mark
00 holds, 11 toggles.
- (A) is wrong: No.
- (B) is wrong: No.
- (C) is wrong: No.
Re-read: Lesson 6.1.3 — Converting flip-flops; timing and the maximum clock frequency
Q7 Answer: 402 marks
Period 25 ns.
Re-read: Lesson 6.1.3 — Converting flip-flops; timing and the maximum clock frequency
Q8 Answer: 51 mark
3 + 0 + 2.
Re-read: Lesson 6.1.3 — Converting flip-flops; timing and the maximum clock frequency