Data-routing circuits

ACompressed recap

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MUX: Y = Σ mₖ(S)·Iₖ; any n-variable function on a 2ⁿ⁻¹:1 MUX with inputs 0, 1, x, x'; 2ⁿ:1 needs 2ⁿ − 1 two-to-one MUXes. Decoder outputs = minterms; function = decoder + OR; 4-to-16 from five 2-to-4. Priority encoder: Y₁ = D₃ + D₂, Y₀ = D₃ + D₂'D₁, V = OR. Demux = decoder with enable as data. ROM 2ⁿ × m; PLA shares product terms; PAL has a fixed OR.

BMerged rule card

5.2.1 Multiplexers, and implementing functions with them

• 2ⁿ:1 MUX: n selects; Y = Σ mₖ(S)·Iₖ. 2:1: Y = S'I₀ + SI₁.
• Any n-variable function: 2ⁿ:1 MUX with the truth table on the inputs, or 2ⁿ⁻¹:1 MUX with inputs from {0, 1, x, x'}.
• Reading a MUX: sum of select minterms times the inputs.
• 2ⁿ:1 MUX from 2:1 MUXes: 2ⁿ − 1 of them.

5.2.2 Decoders, encoders, priority encoders and demultiplexers

• n-to-2ⁿ decoder: Yₖ = mₖ (with enable). Function = decoder + OR of its minterm outputs.
• Decoder trees: 4-to-16 from five 2-to-4 decoders, or from two 3-to-8 with enables.
• Encoder 2ⁿ-to-n assumes one active input. Priority encoder (4-input): Y₁ = D₃ + D₂, Y₀ = D₃ + D₂'D₁, V = OR of all.
• Demultiplexer = decoder with the enable as data.

5.2.3 ROMs and PLAs: programmable logic

• ROM: fixed AND (decoder), programmable OR; size 2ⁿ × m bits.
• PLA: programmable AND and OR; count distinct product terms; share terms between outputs.
• PAL: programmable AND, fixed OR (no sharing).

CInterleaved GATE-style questions

Q1MCQ2 marksMUX reading

A 2:1 MUX has S = A, I₀ = B, I₁ = C. The output is:

• (A) AB + A'C
• (B) A'B + AC
• (C) A(B + C)
• (D) B + C

Q2NAT2 marksMUX design

F(A, B, C) = Σm(0, 1, 6) on a 4:1 MUX with selects A (S₁) and B (S₀). How many of the four data inputs are connected to a constant (0 or 1)?

Numerical answer: ________

Q3NAT1 markMUX tree

How many 4:1 MUXes are needed to build a 16:1 MUX as a tree?

Numerical answer: ________

Q4NAT1 markDecoder

How many outputs does a 4-to-16 decoder have?

Numerical answer: ________

Q5MCQ1 markDecoder function

A 3-to-8 decoder and an OR gate of Y₁, Y₂, Y₄, Y₇ implement:

• (A) AB + BC + CA
• (B) ABC
• (C) A + B + C
• (D) A ⊕ B ⊕ C

Q6MCQ1 markPriority

A 4-input priority encoder (D₃ highest) receives 1001. Output Y₁Y₀?

• (A) 11
• (B) 01
• (C) 00
• (D) 10

Q7NAT2 marksROM

A ROM implements a 4-bit × 4-bit unsigned multiplier. How many bits does it store?

Numerical answer: ________

Q8MCQ1 markPLA

In a PLA, minimising the output functions together is useful because:

• (A) the OR array is fixed
• (B) it removes the need for an AND array
• (C) it reduces the number of inputs
• (D) product terms can be shared between outputs

DAnswer Vault