Half adder, full adder and the ripple-carry adder

0 · Recall Warm-up

Answer from memory first. Answers are in the Answer Vault at the bottom.

• Circuit delay is determined by? from Lesson 5.1.1
• A ⊕ B ⊕ C is 1 when? from Lesson 3.2.3
• Carry rule in binary addition? from Lesson 0.1.3

1 · The Hook

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Adding two 32-bit numbers by hand means 32 columns, each adding two bits and a carry. A full adder is one column in hardware; chaining 32 of them gives a 32-bit adder. The catch: each column must wait for the carry from the column to its right, so the carry ripples across, and GATE asks how long that takes.

2 · Predict First

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One column adds bits A and B and an incoming carry C. If A = 1, B = 1, C = 1, what are the sum bit and the outgoing carry?

Make a guess in your head. The answer opens Section 3.

3 · Core Concept

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Predict First — the answer

1 + 1 + 1 = 3 = 11₂ → sum 1, carry 1.

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In plain words

A half adder adds two bits: the sum is their XOR, the carry is their AND. A full adder adds three bits (two digits and a carry in): the sum is the XOR of all three, and the carry out is 1 when at least two of them are 1 (majority). Put n full adders in a row, each passing its carry to the left, and you have an n-bit ripple-carry adder.

1. Half adder

S = A ⊕ B, C = AB.

2. Full adder

Inputs A, B, Cᵢₙ; outputs S, Cₒᵤₜ.

• S = A ⊕ B ⊕ Cᵢₙ (minterms 1, 2, 4, 7).
• Cₒᵤₜ = AB + BCᵢₙ + ACᵢₙ = AB + Cᵢₙ(A ⊕ B) (minterms 3, 5, 6, 7, the majority).
• A full adder = two half adders + an OR gate: the first adds A and B, the second adds Cᵢₙ to that sum, and the OR combines the two carries.

3. Ripple-carry adder (RCA)

n full adders; the carry out of stage i is the carry in of stage i + 1; C₀ is the carry into the LSB stage. Timing: suppose every full adder produces its carry t_c after its inputs are ready and its sum t_s after. Stage i's carry is ready at (i + 1)·t_c, so:

• final carry Cₙ at n·t_c;
• most significant sum Sₙ₋₁ at (n − 1)·t_c + t_s;
• the addition is complete at the larger of the two.

Example: 4-bit RCA with t_c = 2 ns, t_s = 3 ns: C₄ at 8 ns, S₃ at 6 + 3 = 9 ns. Delay grows linearly with n.

4. Subtractors (briefly)

Half subtractor: D = A ⊕ B, borrow = A'B. Full subtractor: D = A ⊕ B ⊕ Bᵢₙ, Bₒᵤₜ = A'B + Bᵢₙ(A ⊕ B)'. In practice subtraction reuses the adder (next lesson).

4 · Visual

A full adder from two half adders (XOR + AND each) and an OR gate: S = A ⊕ B ⊕ Cin, Cout = AB + Cin(A ⊕ B).

A 4-bit ripple-carry adder: each stage waits for the carry from the stage on its right.

5 · Worked Examples

Example 1 Easy

A half adder gets A = 1, B = 1. Outputs?

Solution

S = 0, C = 1.

Example 2 Medium

A full adder gets A = 1, B = 0, Cᵢₙ = 1. Outputs?

Solution

1 + 0 + 1 = 10₂ → S = 0, Cₒᵤₜ = 1.

Example 3 GATE

A 16-bit ripple-carry adder uses full adders with carry delay 2 ns and sum delay 3 ns. When is the most significant sum bit valid?

Solution

15 × 2 + 3 = 33 ns.

6 · GATE Traps

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• Full-adder carry is the majority of A, B, Cᵢₙ, not their AND.
• RCA delay: the last sum needs (n − 1) carries plus one sum delay; the last carry needs n carry delays.
• A half adder has no carry input; you can't chain half adders alone into a multi-bit adder.
• Ripple delay grows linearly with the number of bits.

7 · Memory Hook

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"Sum = XOR of all three, carry = majority. Ripple: (n − 1) carries then a sum."

8 · Connect the Dots

Waiting for the carry to ripple through 32 or 64 stages is slow. The next lesson computes all carries at once (carry lookahead), turns the adder into a subtractor with XOR gates, and builds comparators.

9 · Self-Test

GATE format. Try every question before opening the vault.

Q1MCQ1 markHalf adder

The outputs of a half adder are:

• (A) S = AB, C = A ⊕ B
• (B) S = A + B, C = AB
• (C) S = A ⊙ B, C = A + B
• (D) S = A ⊕ B, C = AB

Q2NAT1 markFull adder

How many of the 8 input combinations of a full adder give Cₒᵤₜ = 1?

Numerical answer: ________

Q3NAT2 marksRipple delay

An 8-bit ripple-carry adder uses full adders with carry delay 3 ns and sum delay 4 ns. When is the final carry C₈ valid (ns)?

Numerical answer: ________

Q4NAT2 marksRipple delay

Same adder (carry delay 3 ns, sum delay 4 ns, 8 bits). When is the most significant sum bit S₇ valid (ns)?

Numerical answer: ________

Q5MCQ1 markBuilding

A full adder can be built from:

• (A) two half adders and an OR gate
• (B) one half adder and an XOR gate
• (C) three AND gates
• (D) two half adders only

10 · Rule Card

• Half adder: S = A ⊕ B, C = AB.
• Full adder: S = A ⊕ B ⊕ Cᵢₙ; Cₒᵤₜ = AB + BCᵢₙ + ACᵢₙ = AB + Cᵢₙ(A ⊕ B); = 2 half adders + OR.
• n-bit RCA: Cₙ at n·t_c; Sₙ₋₁ at (n − 1)·t_c + t_s; delay linear in n.

11 · Concept Ledger

Unlocked in this lesson. From here on, these terms may be used.

half adderfull addersum and carry equationsfull adder from half addersripple-carry addercarry propagation delaytiming of the last sum and carryhalf and full subtractors

12 · Answer Vault