Phase 5 Checkpoint: 15 questions on combinational circuits.
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15 questions · 23 marks · 45 minutes. Negative marking on MCQ only: −1/3 mark for a wrong 1-mark MCQ, −2/3 for a wrong 2-mark MCQ. No negative marking for MSQ or NAT; MSQ has no partial credit.
Q1NAT1 markDelay
A circuit has paths of 5 ns, 7 ns and 6 ns from inputs to output. What is its propagation delay (ns)?
Numerical answer: ________
Q2MCQ1 markHazard
A static-1 hazard in a two-level SOP circuit can be removed by:
- (A) removing an essential prime implicant
- (B) using NOR gates
- (C) adding the consensus term
- (D) adding a flip-flop
Q3NAT1 markHalf adder
How many 2-input gates does a half adder need?
Numerical answer: ________
Q4NAT2 marksRCA
A 12-bit ripple-carry adder: full-adder carry delay 2 ns, sum delay 3 ns. Total time until all outputs (sums and final carry) are valid (ns)?
Numerical answer: ________
Q5MCQ1 markFull adder
A full adder's sum output is:
- (A) A ⊕ B ⊕ Cᵢₙ
- (B) (A ⊕ B)Cᵢₙ
- (C) majority(A, B, Cᵢₙ)
- (D) AB + Cᵢₙ
Q6NAT2 marksCLA
In a carry-lookahead adder, how many AND gates are needed to produce C₅ directly?
Numerical answer: ________
Q7MCQ1 markCLA delay
Why is a (full) carry-lookahead adder faster than a ripple-carry adder?
- (A) it ignores carries
- (B) all carries are computed in parallel from P, G and C₀
- (C) it adds only even bits
- (D) it uses fewer gates
Q8NAT2 marksSubtractor
A 4-bit adder–subtractor with M = 1 gets A = 0111 and B = 0010. What value (decimal) does the 4-bit result have?
Numerical answer: ________
Q9MCQ2 marksMUX
A 4:1 MUX with selects A (S₁), B (S₀) and inputs I₀ = C, I₁ = C', I₂ = C', I₃ = C computes:
- (A) A ⊕ B ⊕ C
- (B) AB + C
- (C) A ⊕ B
- (D) A ⊙ B ⊙ C'
Q10NAT1 markMUX size
How many select lines does a 32:1 MUX have?
Numerical answer: ________
Q11NAT2 marksMUX design
To implement any function of 6 variables with one MUX whose data inputs may be 0, 1, x or x', what is the smallest MUX (number of data inputs)?
Numerical answer: ________
Q12MCQ1 markDecoder
Output Y₆ of a 3-to-8 decoder with inputs A B C equals:
- (A) A + B + C'
- (B) ABC'
- (C) AB'C
- (D) A'BC
Q13NAT2 marksDecoder trees
How many 2-to-4 decoders with enable are needed to build a 4-to-16 decoder?
Numerical answer: ________
Q14NAT2 marksROM
A ROM implements a BCD-to-7-segment decoder (4 inputs, 7 outputs). How many bits does it store?
Numerical answer: ________
Q15NAT2 marksPLA
F₁ = A'B + AC, F₂ = A'B + B'C, F₃ = AC + B'C are realised in a PLA. How many product terms?
Numerical answer: ________
✓Answer Vault
Answer Vault
Try the questions first. Open when you are ready to check.
Q1 Answer: 71 mark
The slowest path.
Re-read: Lesson 5.1.1 — Combinational circuits: analysis, design and propagation delay
Q2 Answer: (C)1 mark
Covers the transition between the two groups.
- (A) is wrong: Changes the function.
- (B) is wrong: Conversion alone doesn't remove it.
- (D) is wrong: No.
Re-read: Lesson 5.1.1 — Combinational circuits: analysis, design and propagation delay
Q3 Answer: 21 mark
One XOR, one AND.
Re-read: Lesson 5.1.2 — Half adder, full adder and the ripple-carry adder
Q4 Answer: 252 marks
S₁₁ at 22 + 3 = 25; C₁₂ at 24.
Re-read: Lesson 5.1.2 — Half adder, full adder and the ripple-carry adder
Q5 Answer: (A)1 mark
Odd parity of the three inputs.
- (B) is wrong: Part of the carry.
- (C) is wrong: That is the carry.
- (D) is wrong: No.
Re-read: Lesson 5.1.2 — Half adder, full adder and the ripple-carry adder
Q6 Answer: 52 marks
One for each product term after G₄.
Re-read: Lesson 5.1.3 — Carry-lookahead adder, adder–subtractor and comparators
Q7 Answer: (B)1 mark
Constant depth instead of a chain.
- (A) is wrong: No.
- (C) is wrong: No.
- (D) is wrong: It uses more gates.
Re-read: Lesson 5.1.3 — Carry-lookahead adder, adder–subtractor and comparators
Q8 Answer: 52 marks
7 − 2.
Re-read: Lesson 5.1.3 — Carry-lookahead adder, adder–subtractor and comparators
Q9 Answer: (A)2 marks
Rows: 00 → C, 01 → C', 10 → C', 11 → C: C flipped when A ⊕ B = 1.
- (B) is wrong: No.
- (C) is wrong: Ignores C.
- (D) is wrong: A three-input XNOR equals the XOR, so this is A ⊕ B ⊕ C' = (A ⊕ B ⊕ C)', the complement.
Re-read: Lesson 5.2.1 — Multiplexers, and implementing functions with them
Q10 Answer: 51 mark
2⁵ = 32.
Re-read: Lesson 5.2.1 — Multiplexers, and implementing functions with them
Q11 Answer: 322 marks
Use 5 variables as selects: 2⁵.
Re-read: Lesson 5.2.1 — Multiplexers, and implementing functions with them
Q12 Answer: (B)1 mark
- (A) is wrong: Maxterm form.
- (C) is wrong: m₅.
- (D) is wrong: m₃.
Re-read: Lesson 5.2.2 — Decoders, encoders, priority encoders and demultiplexers
Q13 Answer: 52 marks
1 + 4.
Re-read: Lesson 5.2.2 — Decoders, encoders, priority encoders and demultiplexers
Q14 Answer: 1122 marks
16 × 7.
Re-read: Lesson 5.2.3 — ROMs and PLAs: programmable logic
Q15 Answer: 32 marks
A'B, AC, B'C, each shared.
Re-read: Lesson 5.2.3 — ROMs and PLAs: programmable logic