Asynchronous (ripple) counters and mod-N counters

0 · Recall Warm-up

Answer from memory first. Answers are in the Answer Vault at the bottom.

• States of an n-bit Johnson counter? from Lesson 6.2.1
• T flip-flop with T = 1 does what at each edge? from Lesson 6.1.2
• Minimum flip-flops for 2ⁿ states? from Lesson 0.1.1

1 · The Hook

🎣

A T flip-flop that toggles on every clock edge produces a square wave at half the clock frequency. Feed that wave as the clock of a second toggling flip-flop and you get a quarter, then an eighth… Read the outputs together and they count in binary. That is the ripple counter: very few gates, but each stage waits for the one before, and GATE asks how slow that makes it, and how to cut the count short (mod-N).

2 · Predict First

🤔

A 1 MHz clock drives a toggling flip-flop Q₀, whose output clocks a second toggling flip-flop Q₁, which clocks a third, Q₂. What is the frequency of Q₂?

Make a guess in your head. The answer opens Section 3.

3 · Core Concept

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Predict First — the answer

Each stage halves: 500 kHz, 250 kHz, 125 kHz.

🗣️

In plain words

In an asynchronous (ripple) counter only the first flip-flop gets the real clock; every other flip-flop is clocked by the output of the previous one. Each flip-flop toggles when its clock input falls, so the outputs count up in binary. Because the change ripples through the stages one after another, the count is only correct after all of them have settled.

1. Ripple up counter

n T flip-flops with T = 1, negative-edge triggered, flip-flop i clocked by Qᵢ₋₁ (FF0 by the clock):

• Q₀ toggles on every clock fall; Q₁ when Q₀ falls (1 → 0); and so on: Q₂Q₁Q₀ = 000, 001, 010, …, 111, 000.
• n flip-flops → mod-2ⁿ. Frequency at Qₖ = f_clock / 2ᵏ⁺¹.
• Down counter: clock each stage from the previous Q' instead (or use positive-edge flip-flops clocked by Q).

2. Ripple delay

After a clock edge, the worst case (e.g. 0111 → 1000) changes every stage one after the other: settling time n × t_pd. The clock period must be at least that to read a correct count: f_max = 1/(n × t_pd) (plus any decoding delay). 4 stages of 10 ns → 40 ns → 25 MHz.

3. Mod-N ripple counters

Count 0 … N − 1 using ⌈log₂ N⌉ flip-flops and clear all flip-flops (asynchronously) the moment the count reaches N.

• Mod-10 (decade): clear when the count reaches 1010 → detect Q₃ AND Q₁ (a NAND driving active-low clears).
• Mod-6: clear at 110 → detect Q₂ AND Q₁.
• The state N appears for a moment (a glitch state) before the clear takes effect.
• Only the 1-bits of N need to be detected, because N is the first count where they are all 1.

4 · Visual

A 3-bit ripple up counter (negative-edge flip-flops): Q0 toggles at each falling clock edge, Q1 when Q0 falls, Q2 when Q1 falls. Delays are ignored here.

5 · Worked Examples

Example 1 Easy

How many flip-flops does a mod-12 counter need?

Solution

⌈log₂ 12⌉ = 4.

Example 2 Medium

A 5-bit ripple counter uses flip-flops with t_pd = 8 ns. Maximum clock frequency for a correct count?

Solution

5 × 8 = 40 ns → 25 MHz.

Example 3 GATE

A mod-6 ripple counter clears all flip-flops when the count reaches 6. Which outputs feed the clear gate?

Solution

6 = 110 → Q₂ and Q₁.

6 · GATE Traps

⚠️

• Ripple counters are asynchronous: only the first stage sees the system clock.
• Settling time grows with the number of stages (n × t_pd).
• Mod-N needs ⌈log₂ N⌉ flip-flops; reset at N (not N − 1) when using an asynchronous clear.
• Frequency at the k-th output (k = 0 first) is f/2ᵏ⁺¹.

7 · Memory Hook

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"Each stage halves the frequency. Ripple waits n × t_pd. Mod-N: clear when the 1-bits of N are all 1."

8 · Connect the Dots

Ripple counters are cheap but slow and glitchy. The next lesson gives every flip-flop the same clock and computes its inputs with logic: synchronous counters, including how to design one for any sequence.

9 · Self-Test

GATE format. Try every question before opening the vault.

Q1NAT1 markFlip-flops

How many flip-flops are needed for a mod-20 counter?

Numerical answer: ________

Q2NAT1 markFrequency

A 2 MHz clock drives a 4-bit ripple counter. What is the frequency of the last output Q₃, in kHz?

Numerical answer: ________

Q3NAT2 marksRipple delay

An 8-bit ripple counter uses flip-flops with 5 ns propagation delay. What is the maximum clock frequency for reading a settled count, in MHz?

Numerical answer: ________

Q4MCQ1 markMod-10

A decade (mod-10) ripple counter resets when the count reaches 10. The reset gate detects:

• (A) Q₃, Q₂, Q₁ and Q₀
• (B) Q₃ and Q₀
• (C) Q₂ and Q₁
• (D) Q₃ and Q₁

Q5MCQ1 markAsynchronous

In a ripple counter:

• (A) all flip-flops receive the external clock
• (B) all flip-flops change at the same instant
• (C) only the first flip-flop receives the external clock
• (D) no clock is used

10 · Rule Card

• Ripple up counter: toggling flip-flops, each clocked by the previous output (negative edge); mod-2ⁿ; frequency halves per stage.
• Settling n × t_pd; f_max = 1/(n·t_pd).
• Mod-N: ⌈log₂ N⌉ flip-flops; asynchronous clear when the count reaches N (detect N's 1-bits); brief glitch state N.
• Down counter: clock from Q' (or opposite edge).

11 · Concept Ledger

Unlocked in this lesson. From here on, these terms may be used.

asynchronous counterripple up counterripple down counterfrequency divisionripple delaymaximum count frequencymod-N counter by clearingdecade counterglitch stateflip-flops needed for mod-N

12 · Answer Vault