Phase 6 Checkpoint: 15 questions on latches, flip-flops, counters and state machines.
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15 questions · 21 marks · 45 minutes. Negative marking on MCQ only: −1/3 mark for a wrong 1-mark MCQ, −2/3 for a wrong 2-mark MCQ. No negative marking for MSQ or NAT; MSQ has no partial credit.
Q1MCQ1 markLatch
A NOR SR latch receives S = 0, R = 1. Q becomes:
- (A) unchanged
- (B) 1
- (C) 0
- (D) undefined
Q2MCQ1 markD latch
The main problem with level-sensitive latches in synchronous systems is that:
- (A) they always oscillate
- (B) they need two clocks
- (C) they cannot store a bit
- (D) they are transparent while enabled, so changes can pass through repeatedly
Q3NAT1 markT
A T flip-flop starts at Q = 1 and receives T = 1, 0, 1, 1 at four edges. Final Q?
Numerical answer: ________
Q4NAT2 marksJK
A JK flip-flop at Q = 0 receives (J, K) = (1, 1), (0, 1), (1, 0), (1, 1), (0, 0). Final Q?
Numerical answer: ________
Q5MCQ1 markExcitation
For a T flip-flop, the transition 1 → 1 requires:
- (A) T = 1
- (B) T = x
- (C) T = 0
- (D) impossible
Q6MCQ1 markConversion
An SR flip-flop is made to behave like a D flip-flop by connecting:
- (A) S = 1, R = D
- (B) S = R = D
- (C) S = D', R = D
- (D) S = D, R = D'
Q7NAT2 marksFrequency
t_pd = 2.5 ns, logic delay 6 ns, setup 1.5 ns. Maximum clock frequency (MHz)?
Numerical answer: ________
Q8NAT1 markRing
How many flip-flops does a ring counter with 10 states need?
Numerical answer: ________
Q9MCQ1 markJohnson
A 3-bit Johnson counter starts at 000. The state after 3 clocks is:
- (A) 111
- (B) 011
- (C) 001
- (D) 110
Q10NAT2 marksRipple
A 6-bit ripple counter with 4 ns flip-flops is read by logic that takes 6 ns more. Maximum clock frequency for correct readings (MHz)?
Numerical answer: ________
Q11NAT1 markFrequency division
How many toggling flip-flops in a chain divide a clock frequency by 64?
Numerical answer: ________
Q12MCQ2 marksAnalysis
A 2-bit synchronous counter uses D flip-flops with D₁ = Q₀ and D₀ = Q₁'. Starting at 00, the sequence is:
- (A) 00, 01, 10, 11, 00
- (B) 00, 01, 11, 10, 00
- (C) 00, 10, 01, 00
- (D) 00, 11, 00
Q13NAT2 marksLock-out
For the counter D₂ = Q₁, D₁ = Q₀, D₀ = Q₂' (state Q₂Q₁Q₀), how many of the 8 states are outside the main 6-state cycle?
Numerical answer: ________
Q14NAT2 marksDetector
The non-overlapping Mealy 101 detector receives 1 0 1 0 1 1 0 1. How many 1s does it output?
Numerical answer: ________
Q15NAT1 markFlip-flops
A Moore machine has 12 states. Minimum number of flip-flops?
Numerical answer: ________
✓Answer Vault
Answer Vault
Try the questions first. Open when you are ready to check.
Q1 Answer: (C)1 mark
Reset.
- (A) is wrong: Hold needs both 0.
- (B) is wrong: Set needs S = 1.
- (D) is wrong: Only for S = R = 1.
Re-read: Lesson 6.1.1 — Latches: the SR latch and the gated D latch
Q2 Answer: (D)1 mark
Transparency during the enable.
- (A) is wrong: No.
- (B) is wrong: No.
- (C) is wrong: They do store.
Re-read: Lesson 6.1.1 — Latches: the SR latch and the gated D latch
Q3 Answer: 01 mark
0, 0, 1, 0.
Re-read: Lesson 6.1.2 — Flip-flops: SR, D, JK and T; characteristic and excitation tables
Q4 Answer: 02 marks
1, 0, 1, 0, 0.
Re-read: Lesson 6.1.2 — Flip-flops: SR, D, JK and T; characteristic and excitation tables
Q5 Answer: (C)1 mark
Hold.
- (A) is wrong: Toggles to 0.
- (B) is wrong: T matters.
- (D) is wrong: No.
Re-read: Lesson 6.1.2 — Flip-flops: SR, D, JK and T; characteristic and excitation tables
Q6 Answer: (D)1 mark
Set when D = 1, reset when D = 0.
- (A) is wrong: Forbidden when D = 1.
- (B) is wrong: S = R = 1 is forbidden.
- (C) is wrong: Inverted.
Re-read: Lesson 6.1.3 — Converting flip-flops; timing and the maximum clock frequency
Q7 Answer: 1002 marks
Period 10 ns.
Re-read: Lesson 6.1.3 — Converting flip-flops; timing and the maximum clock frequency
Q8 Answer: 101 mark
One per state.
Re-read: Lesson 6.2.1 — Registers, shift registers, ring and Johnson counters
Q9 Answer: (A)1 mark
000, 100, 110, 111.
- (B) is wrong: After 4.
- (C) is wrong: After 5.
- (D) is wrong: After 2.
Re-read: Lesson 6.2.1 — Registers, shift registers, ring and Johnson counters
Q10 Answer: 33.33 to 33.342 marks
6 × 4 + 6 = 30 ns.
Re-read: Lesson 6.2.2 — Asynchronous (ripple) counters and mod-N counters
Q11 Answer: 61 mark
2⁶.
Re-read: Lesson 6.2.2 — Asynchronous (ripple) counters and mod-N counters
Q12 Answer: (B)2 marks
A 2-bit Johnson counter.
- (A) is wrong: That is binary counting.
- (C) is wrong: No.
- (D) is wrong: No.
Re-read: Lesson 6.2.3 — Synchronous counters: analysis and design
Q13 Answer: 22 marks
010 and 101.
Re-read: Lesson 6.2.3 — Synchronous counters: analysis and design
Q14 Answer: 22 marks
Detections at positions 3 and 8.
Re-read: Lesson 6.2.4 — Finite state machines: Mealy and Moore, sequence detectors, state minimisation
Q15 Answer: 41 mark
2⁴ = 16 ≥ 12.
Re-read: Lesson 6.2.4 — Finite state machines: Mealy and Moore, sequence detectors, state minimisation