Flip-flops: SR, D, JK and T; characteristic and excitation tables

0 · Recall Warm-up

Answer from memory first. Answers are in the Answer Vault at the bottom.

• Which NOR SR latch input is forbidden? from Lesson 6.1.1
• What does a gated D latch do while enabled? from Lesson 6.1.1
• XOR of a bit with 1? from Lesson 3.1.2

1 · The Hook

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A clock in a computer ticks hundreds of millions of times per second, and on each rising edge every flip-flop takes one snapshot of its input. Between edges nothing changes. Four kinds of flip-flop exist (D, T, JK, SR); GATE asks you to trace them, to write their equations and to fill in their excitation tables, which drive every counter design.

2 · Predict First

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A flip-flop has one input T. When T = 1 its output flips at each clock edge; when T = 0 it stays. Starting from Q = 0 with T = 1, what are Q after four clock edges?

Make a guess in your head. The answer opens Section 3.

3 · Core Concept

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Predict First — the answer

1, 0, 1, 0: it toggles (halving the clock frequency).

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In plain words

A flip-flop is a one-bit memory that changes only at a clock edge. Each type has a rule for the next value Q⁺ from the current Q and its inputs: D copies D, T toggles when T = 1, JK is like SR but J = K = 1 toggles instead of being forbidden. The excitation table answers the reverse question: "to go from this Q to that Q⁺, what must the inputs be?"

1. Edge triggering

A positive-edge-triggered flip-flop samples its inputs at the instant the clock goes 0 → 1 and ignores them the rest of the time. (Negative-edge: at 1 → 0.)

2. The four flip-flops

3. Excitation tables (Q → Q⁺ : required inputs; x = don't care)

Read the JK row 0 → 1 as: J must be 1 (set or toggle both work), K may be anything.

4. Tracing a JK flip-flop

Start Q = 0. Inputs (J, K) at successive edges: (1, 0), (0, 0), (1, 1), (1, 1), (0, 1), (1, 1) → Q = 1, 1, 0, 1, 0, 1.

5. Race-around and master–slave

A level-triggered JK latch with J = K = 1 toggles again and again while the clock stays high (if the pulse is longer than the gate delay): the race-around condition. Fixes: a master–slave JK (master follows while the clock is high, slave copies on the falling edge) or edge triggering.

4 · Visual

The same D drives a D latch (enabled while CLK = 1) and a positive-edge D flip-flop. The latch follows D during each high phase; the flip-flop changes only at the dashed rising edges.

5 · Worked Examples

Example 1 Easy

A T flip-flop has Q = 1 and T = 1 at a clock edge. Q⁺?

Solution

Toggle → 0.

Example 2 Medium

A JK flip-flop has Q = 1, J = 0, K = 1. Q⁺?

Solution

Reset → 0.

Example 3 GATE

Using the excitation table, what J and K are needed for a JK flip-flop to go from Q = 1 to Q⁺ = 1?

Solution

J = x, K = 0.

6 · GATE Traps

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• JK with J = K = 1 toggles; SR with S = R = 1 is forbidden.
• Excitation tables are read from the transition (Q → Q⁺) to the inputs, the reverse of characteristic tables.
• T flip-flop: T = 0 holds (doesn't reset).
• Edge-triggered flip-flops ignore input changes between edges.

7 · Memory Hook

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"D copies, T toggles, JK = SR with 11 → toggle. Excitation: 0→1 needs J = 1, 1→0 needs K = 1, the other is x."

8 · Connect the Dots

Sometimes you have one kind of flip-flop but need another, and every flip-flop needs its input settled before the clock edge. The next lesson converts flip-flops into each other and works out the fastest safe clock.

9 · Self-Test

GATE format. Try every question before opening the vault.

Q1NAT2 marksJK trace

A JK flip-flop starts at Q = 0. At four successive clock edges, (J, K) = (1, 1), (1, 1), (0, 0), (1, 0). What is Q after the fourth edge?

Numerical answer: ________

Q2MCQ1 markEquation

The characteristic equation of a JK flip-flop is:

• (A) Q⁺ = J ⊕ K
• (B) Q⁺ = JQ' + K'Q
• (C) Q⁺ = JK + Q
• (D) Q⁺ = J + K'Q

Q3MCQ1 markExcitation

To make a JK flip-flop go from Q = 0 to Q⁺ = 1, the inputs must be:

• (A) J = 0, K = x
• (B) J = x, K = 1
• (C) J = 1, K = 1 only
• (D) J = 1, K = x

Q4NAT1 markT flip-flop

A T flip-flop with T = 1 starts at Q = 0. How many times is Q = 1 after each of 7 clock edges?

Numerical answer: ________

Q5MCQ1 markRace-around

The race-around condition occurs in:

• (A) an SR latch with S = R = 0
• (B) an edge-triggered D flip-flop
• (C) a level-triggered JK latch with J = K = 1 and a long clock pulse
• (D) a T flip-flop with T = 0

10 · Rule Card

• Edge-triggered: inputs sampled only at the clock edge.
• D: Q⁺ = D. T: Q⁺ = T ⊕ Q. JK: Q⁺ = JQ' + K'Q (11 toggles). SR: Q⁺ = S + R'Q, SR = 0.
• Excitation (Q → Q⁺): D = Q⁺; T = Q ⊕ Q⁺; JK: 0→0 0x, 0→1 1x, 1→0 x1, 1→1 x0; SR: 0x, 10, 01, x0.
• Race-around in level-triggered JK with J = K = 1; fixed by master–slave or edge triggering.

11 · Concept Ledger

Unlocked in this lesson. From here on, these terms may be used.

clock edgepositive and negative edge triggeringD flip-flopT flip-flopJK flip-flopSR flip-flopcharacteristic tables and equationsexcitation tablesrace-around conditionmaster–slave flip-flop

12 · Answer Vault