Latches: the SR latch and the gated D latch

0 · Recall Warm-up

Answer from memory first. Answers are in the Answer Vault at the bottom.

• What makes a circuit sequential rather than combinational? from Lesson 5.1.1
• NOR output when any input is 1? from Lesson 3.1.1
• What is a static-1 hazard? from Lesson 5.1.1

1 · The Hook

🎣

Press a doorbell and it rings only while you hold the button; press a light switch and the light stays on after you let go. The switch remembers. To remember a bit, a circuit feeds its output back into its own input. The simplest such circuit, two cross-coupled NOR gates, is the SR latch: the ancestor of every register and memory cell.

2 · Predict First

🤔

Two NOR gates are connected so that each one's output is the other one's input. If one output is 1, what must the other output be (with the extra inputs at 0)?

Make a guess in your head. The answer opens Section 3.

3 · Core Concept

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Predict First — the answer

0: a NOR with a 1 at its input outputs 0, which keeps the first output at 1. The pair is stable and remembers which one is 1.

🗣️

In plain words

A latch is a one-bit memory made of two gates feeding each other. S (set) forces the stored bit Q to 1, R (reset) forces it to 0, and when both are inactive the latch keeps what it had. A gated D latch adds an enable: while enable is 1 the output follows the data input D; when enable goes to 0 it holds the last value.

1. SR latch with NOR gates (active-high inputs)

Q = (R + Q̄)', Q̄ = (S + Q)'.

2. S̄R̄ latch with NAND gates (active-low inputs)

The inputs work when they are 0: S̄ = 0 sets, R̄ = 0 resets, both 1 holds, both 0 is forbidden (both outputs 1).

3. Gated latches

• Gated SR latch: S and R pass through AND gates with an enable E; with E = 0 the latch holds.
• Gated D latch: S = D·E, R = D'·E. With E = 1, Q = D (the latch is transparent); with E = 0, Q holds. No forbidden input combination.

4. Why latches are not enough

While E = 1 the output follows every wiggle of D. In a system where outputs feed back to inputs through logic, a transparent latch can let a value race around the loop several times in one enable pulse. Phase 6 therefore uses edge-triggered flip-flops (next lesson), which react only at a clock edge.

4 · Visual

SR latch from two cross-coupled NOR gates: each output feeds back into the other gate. S = 1 sets Q, R = 1 resets it, S = R = 0 holds.

5 · Worked Examples

Example 1 Easy

A NOR SR latch has Q = 0. S = 1, R = 0 is applied, then S returns to 0. What is Q?

Solution

Set makes Q = 1; with S = R = 0 it holds 1.

Example 2 Medium

A NAND S̄R̄ latch receives S̄ = 1, R̄ = 0. What is Q?

Solution

R̄ = 0 is active (reset) → Q = 0.

Example 3 GATE

For a gated D latch with E = 1, D changes 0 → 1 → 0. What does Q do?

Solution

It follows D: 0 → 1 → 0 (transparent).

6 · GATE Traps

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• NOR latch: inputs active-high, S = R = 1 forbidden. NAND latch: inputs active-low, S̄ = R̄ = 0 forbidden.
• A D latch has no forbidden state, but it is transparent while enabled.
• "Hold" means the output stays at whatever it was, not 0.
• Latches are level-sensitive; flip-flops are edge-sensitive.

7 · Memory Hook

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"Two gates hugging each other remember a bit. NOR: 1s act. NAND: 0s act. D latch: see-through while enabled."

8 · Connect the Dots

The transparency problem is solved by flip-flops, which change only at the instant the clock rises. The next lesson covers the four flip-flop types (SR, D, JK, T) and their characteristic and excitation tables.

9 · Self-Test

GATE format. Try every question before opening the vault.

Q1MCQ1 markNOR latch

In a NOR SR latch, which input combination is not allowed?

• (A) S = 0, R = 1
• (B) S = 0, R = 0
• (C) S = 1, R = 0
• (D) S = 1, R = 1

Q2MCQ1 markNAND latch

In a NAND S̄R̄ latch, which input combination holds the stored value?

• (A) S̄ = 1, R̄ = 0
• (B) S̄ = 0, R̄ = 1
• (C) S̄ = 1, R̄ = 1
• (D) S̄ = 0, R̄ = 0

Q3NAT1 markHold

A NOR SR latch stores Q = 1. The inputs are S = 0, R = 0 for a while. What is Q?

Numerical answer: ________

Q4MCQ1 markD latch

A gated D latch with enable E = 0:

• (A) holds its output whatever D does
• (B) toggles
• (C) resets to 0
• (D) copies D

Q5NAT1 markD latch

A gated D latch has E = 1 and D = 0. What is Q?

Numerical answer: ________

10 · Rule Card

• Latch = cross-coupled gates with feedback; stores one bit; level-sensitive.
• NOR SR latch: S = 1 sets, R = 1 resets, 00 holds, 11 forbidden.
• NAND S̄R̄ latch: 0 sets/resets (active-low), 11 holds, 00 forbidden.
• Gated D latch: E = 1 → Q = D (transparent); E = 0 → hold.

11 · Concept Ledger

Unlocked in this lesson. From here on, these terms may be used.

feedback and memorySR latch with NOR gatesforbidden inputNAND latch with active-low inputsgated SR latchgated D latchtransparencylevel sensitivity

12 · Answer Vault