Converting flip-flops; timing and the maximum clock frequency

0 · Recall Warm-up

Answer from memory first. Answers are in the Answer Vault at the bottom.

• Excitation of a T flip-flop for Q → Q⁺? from Lesson 6.1.2
• JK equation? from Lesson 6.1.2
• Delay of a circuit? from Lesson 5.1.1

1 · The Hook

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A lab has only D flip-flops but the design calls for JK. A few gates in front of the D input fix that. And no matter which flip-flop you use, the signal must cross the logic between two flip-flops before the next clock edge: that sets the maximum clock frequency, a standard GATE numerical.

2 · Predict First

🤔

A flip-flop's output appears 4 ns after the clock edge; the logic after it takes 10 ns; the next flip-flop needs its input steady 2 ns before the next edge. What is the shortest safe clock period?

Make a guess in your head. The answer opens Section 3.

3 · Core Concept

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Predict First — the answer

4 + 10 + 2 = 16 ns (62.5 MHz).

🗣️

In plain words

To build flip-flop X from flip-flop Y, ask for every (Q, X-inputs) combination what Q⁺ should be, look up which Y-inputs give that transition (Y's excitation table), and simplify. For timing, the clock period must be long enough for the slowest signal to leave one flip-flop, pass through the logic and arrive early enough (setup time) at the next flip-flop.

1. Conversions (method)

• Write X's characteristic table: columns Q, X-inputs, Q⁺.
• For each row, use Y's excitation table to get Y's inputs.
• Minimise Y's inputs as functions of Q and X's inputs.

Standard results:

2. Timing parameters

• Setup time t_su: the input must be stable this long before the clock edge.
• Hold time t_h: the input must stay stable this long after the edge.
• Clock-to-Q (propagation) delay t_pd: time from the edge to the new output.

3. Maximum clock frequency

For a path from one flip-flop through combinational logic to another: T_min = t_pd(FF) + t_comb(max) + t_su (+ clock skew if given), f_max = 1 / T_min. Example: t_pd = 4 ns, t_comb = 10 ns, t_su = 2 ns → 16 ns → 62.5 MHz. Hold check: t_pd(FF) + t_comb(min) ≥ t_h, otherwise the new data overruns the old one too soon.

4 · Visual

One clock period must cover: Q1 settling after the edge (t_pd), the logic computing D2 (t_comb), and D2 being stable for the setup time before the next edge.

5 · Worked Examples

Example 1 Easy

How do you make a T flip-flop from a JK flip-flop?

Solution

Tie J = K = T.

Example 2 Medium

Make a T flip-flop from a D flip-flop.

Solution

D = T ⊕ Q (T = 0 keeps Q, T = 1 gives Q').

Example 3 GATE

t_pd = 3 ns, worst logic delay 5 ns, setup 2 ns. Maximum clock frequency?

Solution

T = 10 ns → 100 MHz.

6 · GATE Traps

⚠️

• Setup time adds to the period; hold time does not (it constrains the minimum path).
• Use the longest logic path for f_max and the shortest for the hold check.
• D from JK: J = D, K = D' (not K = D).
• 1/(ns) gives GHz; 1000/(period in ns) gives MHz.

7 · Memory Hook

🧠

"Conversion: wanted next state → available excitation → K-map. Period ≥ t_pd + logic + setup."

8 · Connect the Dots

Chapter 6.1 is complete. Chapter 6.2 puts several flip-flops together: registers and shift registers first, then counters and finally general state machines.

9 · Self-Test

GATE format. Try every question before opening the vault.

Q1MCQ1 markConversion

To convert a JK flip-flop into a D flip-flop, connect:

• (A) J = D, K = D
• (B) J = 1, K = D
• (C) J = D', K = D
• (D) J = D, K = D'

Q2MCQ1 markConversion

A D flip-flop behaves as a T flip-flop if D is connected to:

• (A) T + Q
• (B) T
• (C) T ⊕ Q
• (D) TQ

Q3NAT1 markClock period

t_pd = 5 ns, logic delay 12 ns, setup 3 ns. Minimum clock period (ns)?

Numerical answer: ________

Q4NAT2 marksFrequency

t_pd = 2 ns, logic delay 6 ns, setup 1 ns, clock skew 1 ns. Maximum clock frequency in MHz?

Numerical answer: ________

Q5MCQ1 markHold

The hold-time condition compares the hold time with:

• (A) the shortest path delay from one flip-flop to the next
• (B) the clock period
• (C) the longest path delay
• (D) the setup time

10 · Rule Card

• Conversion: X's characteristic table → Y's excitation → minimise. D from JK: J = D, K = D'; T from JK: J = K = T; T from D: D = T ⊕ Q; JK from D: D = JQ' + K'Q.
• Setup before the edge, hold after, t_pd from edge to output.
• T_min = t_pd + t_comb(max) + t_su (+ skew); f_max = 1/T_min. Hold: t_pd + t_comb(min) ≥ t_h.

11 · Concept Ledger

Unlocked in this lesson. From here on, these terms may be used.

flip-flop conversion methodstandard conversionssetup timehold timeclock-to-Q delayminimum clock periodmaximum clock frequencyclock skewhold-time check

12 · Answer Vault