0 · Recall Warm-up
Answer from memory first. Answers are in the Answer Vault at the bottom.
- SSTF total for the running queue? from Lesson 6.2.2
- Average rotational latency at 6000 rpm? from Lesson 6.2.1
- What is an interrupt? from Lesson 0.1.2
1 · The Hook
A kettle can be watched until it boils (wasting your time), or it can whistle when ready (you do other things meanwhile). Better still, ask a helper to pour all the cups and tell you when they're done. Those are programmed I/O, interrupt-driven I/O and DMA. GATE asks what fraction of the CPU each one uses.
2 · Predict First
Try the questions first. Open when you are ready to check.
A device delivers one byte every 100 µs. Handling an interrupt costs the CPU 4 µs. If the CPU waits in a loop for each byte, it is busy 100% of the time. With interrupts, what fraction is it busy?
Make a guess in your head. The answer opens Section 3.
3 · Core Concept
Predict First — the answer
4 µs out of every 100 µs = 4%: 25 times better.
In plain words
A device controller has a few registers (data, status, command). The CPU can keep checking the status register (polling), let the device interrupt when it's ready, or let a DMA controller move a whole block into memory by itself and interrupt only once at the end.
1. Programmed I/O (polling)
The CPU loops reading the status register until the device is ready, then moves each byte itself. Simple, but the CPU is busy waiting for the whole transfer.
2. Interrupt-driven I/O
The CPU starts the operation and does other work; the device interrupts when it has data (or finished). The CPU pays an interrupt overhead per transfer unit. CPU fraction used = (transfers per second) × (overhead per transfer). Example: 2,000,000 bytes/s moved as 4-byte words → 500,000 interrupts/s; at 1 µs each → 50% of the CPU.
3. Direct memory access (DMA)
- The CPU tells the DMA controller: source, destination, byte count. The DMA controller moves the whole block between device and memory and interrupts the CPU once per block.
- While copying, the DMA controller uses the memory bus, sometimes delaying the CPU's own memory accesses: cycle stealing.
- CPU cost per block = setup + one interrupt. Example: 2,000,000 B/s in 4,000-byte blocks → 500 blocks/s; at 20 µs each → 1% of the CPU.
- Cycle-stealing fraction = (words per second) × (memory cycle time). 500,000 words/s × 100 ns = 5%.
4. Buffering, caching, spooling
- Buffer: memory holding data in transit (e.g. speed mismatch between a modem and a disk). Double buffering: fill one buffer while the other is being processed.
- Cache: a fast copy of data kept for reuse (not the only copy).
- Spooling: a queue of complete jobs for a device that can't interleave, like a printer: each print job is saved to disk and printed in turn.
5. Blocking, non-blocking and asynchronous calls
- Blocking: the process waits until the I/O completes (simplest; the process goes to the Waiting state).
- Non-blocking: returns at once with whatever is available.
- Asynchronous: returns at once; the process is told later when the full transfer finishes.
4 · Visual
Who moves the data, and how often is the CPU disturbed?
Programmed I/O : CPU polls + moves every byte CPU busy 100% of the transfer
Interrupt I/O : device interrupts per byte/word CPU pays overhead per unit
DMA : DMA controller moves the block CPU pays setup + 1 interrupt per block
(steals memory cycles meanwhile)
5 · Worked Examples
Example 1 Easy
A device produces 10,000 bytes per second, byte by byte. Interrupt overhead is 4 µs. Fraction of CPU time used in interrupt mode?
Solution
10,000 × 4 µs = 40,000 µs per second = 4%.
Example 2 Medium
In the Easy example, how many times better is interrupt mode than programmed (polling) mode, where the CPU is busy for the whole transfer?
Solution
100% / 4% = 25 times.
Example 3 GATE
A DMA controller transfers 4-byte words at 2,000,000 bytes/s, stealing one 100 ns memory cycle per word. What percentage of memory cycles does the CPU lose?
Solution
500,000 words/s × 100 ns = 0.05 s per second = 5%.
6 · GATE Traps
- Interrupt cost scales with the number of transfers, not bytes, if each interrupt moves a word or block.
- DMA interrupts once per block, not per byte.
- Spooling ≠ buffering: spooling queues whole jobs for a non-sharable device.
- Units: 1 µs = 10⁻⁶ s; 1 ns = 10⁻⁹ s.
7 · Memory Hook
"Poll = watch the kettle; interrupt = it whistles; DMA = a helper pours and tells you once."
8 · Connect the Dots
Phase 6 is complete, and with it the whole syllabus. Phase 7 puts everything together: the master rule sheet, mixed practice, the GATE pattern drill and the final test.
9 · Self-Test
GATE format. Try every question before opening the vault.
Q1 · NAT · 1 mark(s) — Interrupt mode
A device produces 20,000 bytes per second, byte by byte; interrupt overhead 5 µs. Percentage of CPU time used?
Numerical answer: ________
Q2 · NAT · 2 mark(s) — Gain
A device delivers 10,000 bytes per second (one at a time). Programmed I/O keeps the CPU busy for the whole transfer; interrupt overhead is 4 µs per byte. How many times better is interrupt mode?
Numerical answer: ________
Q3 · NAT · 2 mark(s) — DMA blocks
A device transfers 2,000,000 bytes per second using DMA blocks of 4,000 bytes; each block costs the CPU 20 µs (setup and interrupt). Percentage of CPU time used?
Numerical answer: ________
Q4 · MCQ · 1 mark(s) — Spooling
Several processes print at the same time, and each document comes out whole, one after another. This is achieved by:
- (A) polling
- (B) caching
- (C) double buffering
- (D) spooling
Q5 · MCQ · 1 mark(s) — DMA
With DMA, the CPU is interrupted:
- (A) once when the whole block has been transferred
- (B) never
- (C) for every word
- (D) for every byte
10 · Rule Card
- Programmed I/O: CPU polls and moves data (busy waiting).
- Interrupt I/O: CPU fraction = transfers/s × overhead per transfer.
- DMA: one interrupt per block; cycle stealing fraction = words/s × memory cycle.
- Buffer (in transit), double buffering, cache (copy for reuse), spool (queue of jobs for a non-sharable device).
- Blocking, non-blocking, asynchronous I/O calls.
11 · Concept Ledger
Unlocked in this lesson. From here on, these terms may be used.
device controllerstatus/data/command registersprogrammed I/O (polling)interrupt-driven I/Ointerrupt overheaddirect memory accesscycle stealingbufferingdouble bufferingcachingspoolingblocking, non-blocking and asynchronous I/O
12 · Answer Vault
Try the questions first. Open when you are ready to check.
🔐 Open the Answer Vault
Recall Warm-up
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- 5 ms.
- A signal from hardware that makes the CPU run a handler.
Self-Test
Q1 Answer: 10 · 1 mark(s)
20,000 × 5 µs = 0.1 s per second.
Re-read: Lesson 6.2.3 — I/O techniques: programmed I/O, interrupts, DMA, buffering and spooling
Q2 Answer: 25 · 2 mark(s)
100 µs per byte vs 4 µs.
Re-read: Lesson 6.2.3 — I/O techniques: programmed I/O, interrupts, DMA, buffering and spooling
Q3 Answer: 1 · 2 mark(s)
500 blocks × 20 µs = 10 ms per second.
Re-read: Lesson 6.2.3 — I/O techniques: programmed I/O, interrupts, DMA, buffering and spooling
Q4 Answer: (D) · 1 mark(s)
Jobs are queued on disk for the printer.
- (A) is wrong: Checking a status register.
- (B) is wrong: Caches copy data for reuse.
- (C) is wrong: Overlaps producing and consuming.
Re-read: Lesson 6.2.3 — I/O techniques: programmed I/O, interrupts, DMA, buffering and spooling
Q5 Answer: (A) · 1 mark(s)
The controller moves the block itself.
- (B) is wrong: It must learn the transfer finished.
- (C) is wrong: Same.
- (D) is wrong: That is interrupt-driven I/O.
Re-read: Lesson 6.2.3 — I/O techniques: programmed I/O, interrupts, DMA, buffering and spooling